An energy-efficient skew compensation technique for high-speed skew-sensitive signaling

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 1658-1661

  Wang, Lei ^a  

^a UNIVERSITY OF CONNECTICUT   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT PERFORMANCE; CMOS PROCESS; COMPENSATION TECHNIQUES; DISTRIBUTED CLOCKS; ENERGY EFFICIENT; ESSENTIAL ELEMENTS; FUTURE TECHNOLOGIES; HIGH-SPEED; ON CHIP INTERCONNECT; POWER REDUCTIONS; SIMULATION RESULT; TIME-VARYING DISTURBANCE;

COMMUNICATION SYSTEMS; ENERGY EFFICIENCY; OPTICAL INTERCONNECTS; TIMING CIRCUITS;

TIME VARYING NETWORKS;

EID: 33947355662     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464923     Document Type: Conference Paper

References (11)

1. A. Deutsch, et al., "On-chip wiring design challenges for gigahertz operation," Proceedings of the IEEE, vol. 89, pp. 529-555, April 2001.
2. E. G. Friedman, "Clock distribution networks in synchronous digital integrated circuits," Proceedings of the IEEE, vol. 88, pp. 665-692, May 2001.
3. L. Wang and N. R. Shanbhag, "Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise," IEEE Trans. on VLSI Systems, vol. 11, pp. 254-269, April 2003.
4. The International Technology Roadmap for Semiconductors: 2003 Edition, URL: http://public.itrs.net/Files/2003ITRS/Home2003.htm.
5. A. Agarwal, V. Zolotov, and D. T. Blaauw, "Statistical clock skew analysis considering intradie-process variations," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 23 , no. 8, pp. 1231 -1242, Aug. 2004.
6. K. Ravindran, A. Kuehlmann, and E. Sentovich, "Multi-domain clock skew scheduling," Proc. International Conference on Computer Aided Design, pp. 801-808, Nov. 2003.
7. J. L. Tsai, T. H. Chen, and C. C. Chen, "Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing," IEEE Trans. on Computer- Aided Design of Integrated Circuits and Systems, vol. 23, no. 4, pp. 565-572, April 2004.
8. S. Tam, S. Rusu, U. Desai, R. Kim, J. Zhang, and I. Young, "Clock generation and distribution for the first IA-64 microprocessor," IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1545-1552, Nov. 2000.
9. L. Wang, E. S. Fetzer, and J. Jones, "The multi-threaded, parity protected, 128word register files on a dual-core Itanium® Architecture Processor," ISSCC 2005, to appear.
10. Berkeley Predictive Technology Model, URL: http://www-device.eecs. berkeley.edu/~ptm.
11. Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," Proc. of IEEE CICC, pp. 201-204, Jun. 2000.