Fabrication and characterization of CMOSFETs on porous silicon for novel device layer transfer

Technical Digest - International Electron Devices Meeting, IEDM

Volumn 2005, Issue , 2005, Pages 679-682

  Sanda, Hiroyuki ^a   McVittie, James ^a   Koto, Makoto ^b   Yamagata, Kenji ^b   Yonehara, Takao ^b   Nishi, Yoshio ^a  

^a Stanford University   (United States)

^b CANON INC   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EPITAXIAL GROWTH; FIELD EFFECT TRANSISTORS; FILM THICKNESS; INTEGRATED CIRCUITS; POROUS SILICON; SINGLE CRYSTALS;

PLASTIC SUBSTRATES; POROUS LAYER SPLITTING; THERMAL COOLING;

MOSFET DEVICES;

EID: 33847760267     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. H.-S.P. Wong, IBM J. R&D, March/May, 2002, pp. 133-168.
2. K.W. Guarini, 3D architechture for semiconductor integration packaging, 2004.
3. S.K. Kim, L. Xue, S. Tiwari, SOI conf., p136, 2004.
4. H. Sanda, J. McVittie, M. Koto, T. Yonehara, Y. Nishi, IMFEDK, p137, 2005.
5. K. Sakaguchi, K. Yanagita, H. Kurisu, H. Suzuki, K. Ohmi, T. Yonehara, SOI conf., p110, 1999.