Branch prediction topologies for SMT architectures

Proceedings - Symposium on Computer Architecture and High Performance Computing

Volumn , Issue , 2005, Pages 118-125

  Dal Pizzol, Guilherme ^a   Navaux, Philippe O A ^a   Pilla, Maurício L ^b  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

^b CATHOLIC UNIVERSITY OF PELOTAS   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; INSTRUMENT CIRCUITS; PARALLEL PROCESSING SYSTEMS; STORAGE ALLOCATION (COMPUTER); TOPOLOGY;

CLOCK RATES; MASKING LATENCY; PREDICTION MODULES; SIMULTANEOUS MULTI-THREADED (SMT) ARCHITECTURES;

COMPUTER ARCHITECTURE;

EID: 33847208200     PISSN: 15506533     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CAHPC.2005.16     Document Type: Conference Paper

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