PEDL (Polymer Encapsulated Dicing Line) technology for copper/low-k dielectrics interconnect

Proceedings of 7th Electronics Packaging Technology Conference, EPTC 2005

Volumn 2, Issue , 2005, Pages 711-715

  Yoon, Seung Wook ^a   Wirtasa, David ^a   Lim, Samuel ^a   Ganesh, V ^a   Viswanath, Akella ^b   Kripesh, Vaidyanathan ^b   Iyer, Mahadevan K ^b  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b INSTITUTE OF HIGH PERFORMANCE COMPUTING   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CRACK PROPAGATION; DELAMINATION; DIELECTRIC DEVICES; ELECTRONICS PACKAGING; FLIP CHIP DEVICES; THERMAL EXPANSION;

DIELECTRICS INTERCONNECT; FLIPCHIP PACKAGING; MOISTURE SENSITIVITY LEVEL (MSL); POLYMER ENCAPSULATED DICING LINE (PEDL);

ELECTRIC POWER SYSTEM INTERCONNECTION;

EID: 33847148009     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Lei L. Mercado, Cindy Goldberg, Shun-Meen Kuo, Tien-Yu Lee and Scott K. Pozder, "Analysis of flipchip packaging challenges on copper/low-k interconnectes," IEEE transactions on device and materials reliability, vol .3, no.4, Dec. 2003
2. International Technology Roadmap for Semiconductors, 2001 and 2003 Update.
3. Akella G.K.Viswanath, Wang Fang, Tai-Chong Chai, Navas Khan, Srinivasamurthy Sampath, "Structural optimization of fine pitch, large die flip chip package," , Electronic Packaging Technology Conference (EPTC) 2004
4. Seung Wook Yoon, Vaidyanathan Kripesh, Li Hongyu,Li Chao Yong, Su Yong Ji Jeffrey and Mahadevan K. Iyer, "Flipchip Bump Integrity with Copper/Ultra Low-k Dielectrics for fine pitch Flipchip Packaging", Proceeding of the 54th Electronic Components Technology Conference(ECTC), Las Vegas, US (2004).