Structural optimization of fine pitch, large die flip chip package

Proceedings of 6th Electronics Packaging Technology Conference, EPTC 2004

Volumn , Issue , 2004, Pages 105-108

  Viswanath, Akella G K ^a   Fang, Wang ^a   Chai, Tai Chong ^b   Khan, Navas ^b   Sampath, Srinivasamurthy ^b  

^a INSTITUTE OF HIGH PERFORMANCE COMPUTING   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

DIES; FLIP CHIP DEVICES; SHEAR STRESS; STRESS CONCENTRATION; SUBSTRATES; THERMOMECHANICAL TREATMENT;

FINE PITCH; SUBSTRATE DESIGN; SUBSTRATE LAYERS; THERMO MECHANICAL ANALYSIS;

STRUCTURAL OPTIMIZATION;

EID: 28444467810     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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