Flipchip Bump Integrity with Copper/Ultra Low-k Dielectrics for Fine pitch Flipchip Packaging

Proceedings - Electronic Components and Technology Conference

Volumn 2, Issue , 2004, Pages 1636-1641

  Yoon, Seung Wook ^a   Kripesh, Vaidyanathan ^a   Yu, Li Hong ^a   Yong, Li Chao ^a   Jeffrey, Su Yong Ji ^a   Iyer, Mahadevan K ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

FLIPCHIP PACKAGING; LOW-K DIELECTRICS; MOORE LAW; TRANSISTOR SCALING;

ADHESION; CAPACITANCE; CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; ENCAPSULATION; FLIP CHIP DEVICES; METALLIZING; ULSI CIRCUITS;

ELECTRONICS PACKAGING;

EID: 10444231179     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. nd Electronic Components & Technology Conference, May 2002, San Diego
2. Members update to wafer technology consortium (WTC)-project-lB, Flip Chip Packaging & Reliability of Cu/Ultra-low k Interconnects, June 2003
3. rd Electronic Components & Technology Conference, May 2003, New Orleans