Thermal cycle reliability of 3D chip stacked package using Pb-free solder bumps: Parameter study by FEM analysis

7th International Conference on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, EuroSimE 2006

Volumn 2006, Issue , 2006, Pages

  Noritake, C ^a,b   Limaye, P ^b   Gonzalez, M ^b   Vandevelde, Bart ^b  

^a DENSO CORPORATION   (Japan)

^b IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; FINITE ELEMENT METHOD; LEAD COMPOUNDS; PRINTED CIRCUIT BOARDS; RELIABILITY; SOLDERED JOINTS; THERMAL CYCLING;

CHIP STACKED PACKAGE; CREEP STRAIN; DAMAGE PARAMETER; THERMO-MECHANICAL RELIABLILITY;

ELECTRONICS PACKAGING;

EID: 33847147249     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESIME.2006.1644002     Document Type: Conference Paper

References (6)

1. Seppo K. Pienimaa et al, " Stacked Modular Package", IEEE Transactions on advanced packaging, Vol.27, No.3, August 2004, pp.461-466
2. Kenji Takahashi et al, "Current status of research and development for three-dimensional chip stack technology", Jpn.J.Appl.Phys., Vol.40, 2001, pp.3032-3037
3. Kazumasa Tanida et al, " Micro Cu bump Interconnection on 3D chip stacking technology", Jpn.J.Apply.Phys., Vol.43, No.4B, 2004, pp.2264-2270
4. Noriaki Sakmoto et al, "Designing and packaging technology of Renesas SIP", International symposium on circuits and systems 2005, Vol.6, pp5926-2929
5. Bart Vandevelde et al, " Thermal cycling reliability of SnAgCu and SnPb solder joints: a comparison or several IC-packages", Proceedings of EuroSIME 2004, pp.565-570
6. Mario Gonzalez et al, " Influence of dielectric materials and via geometry on the thermomechanical behavior of silicon through interconnects", Proceedings of Pan Pacific Microelectronics symposium 2005, pp.9-14