Designing and packaging technology of renesas SIP

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 5926-5929

  Sakamoto, Noriaki ^a   Sugita, Norihiko ^a   Kikuchi, Takafumi ^a   Tanaka, Hideki ^a   Akazawa, Takashi ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AREA REDUCTION; EMI NOISE; INTEGRATED PRODUCTS; PACKAGING TECHNOLOGIES; RENESAS; RENESAS TECHNOLOGIES; SIGNAL INTEGRITY ANALYSIS; STACK STRUCTURE; SYSTEM IN PACKAGE; SYSTEM ON A CHIP;

CHIP SCALE PACKAGES; ELECTROMAGNETIC PULSE; SIGNAL PROCESSING; TECHNOLOGY;

INTERNET PROTOCOLS;

EID: 33847141850     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465988     Document Type: Conference Paper

References (5)

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3. P. Dehkordi, K. Ramamurthi, D. Bouldin, and H. Davidson, Early Cost/Performance Cache Analysis of a Split MCM-Based MicroSparc CPU, Proc. the MCM Conference, Feb. 1996.
4. A. I. Kayssi, K. A. Sakallah, R. B. Brown, R. J. Lomax, T. N. Mudge, and T. R. Huff, Impact of MCMs on System Performance Optimization, Proc. of Multichip Module Workshop, Santa Cruz, pp. 919-922, March 1991.
5. A. Kazama, T. Satoh, Y. Yamaguchi, I. Anjoh, and A. Nishimura, Development of Low-Cost and Highly Reliable Wafer Process Journal of Japan Institute of Electronics Packaging, vol. 5, No. 3, pp. 264-271, May, 2002 (in Japanese).