Conjugate gradient sparse solvers: Performance-power characteristics

20th International Parallel and Distributed Processing Symposium, IPDPS 2006

Volumn 2006, Issue , 2006, Pages

  Malkowski, Korad ^a   Lee, Ingyu ^a   Raghavan, Padma ^a   Irwin, Mary Jane ^a  

^a The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); COMPUTER ARCHITECTURE; COMPUTER SIMULATION; ELECTRIC POWER MEASUREMENT; OPTIMIZATION; RESPONSE TIME (COMPUTER SYSTEMS);

CONJUGATE GRADIENT SPARSE SOLVERS; DYNAMIC VOLTAGE SCALING (DVS); PERFORMANCE-POWER CHARACTERISTICS;

SUPERVISORY AND EXECUTIVE PROGRAMS;

EID: 33847142869     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2006.1639595     Document Type: Conference Paper

References (26)

1. G. Almási, R. Bellofatto, J. Brunheroto, C. Caşcaval, and et al.,. An Overview of the Blue Gene/L System Software Organizaation. In Lecture Notes in Computer Science, Euro-Par 2003 Parallel Processing: 9th International Euro-Par Conference, pages 543-555, January 2003.
2. D. H. Bailey, L. Dagum, E. Barszcz, and H. D. Simon. NAS parallel benchmark results. In Supercomputing '92: Proceedings of the 1992 ACM/IEEE conference on Super computing, pages 386-393, Los Alamitos, CA, USA, 1992. IEEE Computer Society Press.
3. R. Barrett, M. Berry, T. F. Chan, and et al.,. Templates for the Solution of Linear Systems: Building Blocks for Iterative Methods, 2nd Edition. SIAM, 1994.
4. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: a framework for architectural-level power analysis and optimizations. In ISCA '00; Proceedings of the 27th annual international symposium on Computer architecture, pages 83-94. ACM Press, 2000.
5. D. Burger and T. M. Austin. The SimpleScalar tool set, version 2.0. SIGARCH Comput. Archit. News, 25(3): 13-25, 1997.
6. K. Choi, R. Soma, and M. Pedram. Fine-grained dynamic voltage and frequency scaling for precise energy and performance trade-off based on the ratio of off-chip access to on-chip computation times. In DATE '04: Proceedings of the conference on Design, automation and test in Europe, page 10004. IEEE Computer Society, 2004.
7. T. Chung. Computational fluid dynamics. Cambridge University Press, 2002.
8. F. Dahlgren and P. Stenstrm. Evaluation of stride and sequential hardware-based prefetching in shared-memory multiprocessors. IEEE Trans. on Parallel and Distributed Systems, 7(4):385-398, April 1996.
9. J. Dongarra. Top500 list and the LINPACK benchmark. http://www.top500. org/lists/linpack.php.
10. X. Feng, R. Ge, and K. W. Cameron. Power and energy profiling of scientific applications on distributed systems. In IPDPS'05, 2005.
11. J. George. Nested dissection of a regular finite element element mesh. SIAM J. Numerical Analysis, 10:345-363, 1973.
12. J. A. George and J. W.-H. Liu. Computer Solution of Large Sparse Positive Definite Systems. Prentice-Hall Inc., Englewood Cliffs, NJ, 1981.
13. I. D. R. Grimes and J. Lewis. User's guide for the harwellboeing sparse matrix collection (release i). Technical Report TR/PA/92/86, CERFACS, Toulouse Cedex, France, Oct. 1992.
14. W. D. Gropp, D. K. Kaushik, D. E. Keyes, and B. F. Smith. Performance modeling and tuning of an unstructured mesh CFD application. In Proceedings of SC2000. IEEE Computer Society, 2000.
15. E.-J. Im and K. A. Yelick. SPARSITY. http://www.cs.berkely/yelick/ sparsity.
16. M. Inc. Micron Technical Note TN-47-04 Calculating Memory System Power for DDR2, 2004. http://download.micron.com/pdf/technotes/ddr2/TN4704.pdf.
17. T. Ishihara and F. Fallah. A non-uniform cache architecture for low power system design. In ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design, pages 363-368, New York, NY, USA, 2005. ACM Press.
18. N. P. Jouppi. Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. In ISCA '90: Proceedings of the 17th annual international symposium on Computer Architecture, pages 364-373, New York, NY, USA, 1990. ACM Press.
19. N. Kappiah, V. Freeh, D. Lowenthal, and F. Pan. Exploiting slack time in power-aware, high-performance programs. IEEE/ACM Suptercomputing 2005, 2005.
20. C. Lazou. LINPACK results refuel IBM/INTEL chip debate. HPCWire, 12(29), July 2003.
21. W.-F. Lin, S. K. Reinhardt, and D. Burger. Designing a modern memory hierarchy with hardware prefetching. IEEE Trans. Comput., 50(11): 1202-1218, 2001.
22. K. Malkowski, G. Link, P. Raghavan, and M. J. Irwin. Energy-aware memory optimizations for fast sparse scientific computations. Submitted to IEEE Trans. Computer.
23. S. A. McKee, R. H. Klenke, K. L. Wright, W. A. Wulf, M. H. Salinas, J. H. Aylor, and A. P. Batson. Smarter memory: Improving bandwith for streamed references. IEEE Computer, pages 54-63, February 1998.
24. T. B. Team. An overview of the BlueGene/1 Supercomputer. In SC '02: Proceedings of the 2002 ACM/IEEE conference on Supercomputing, pages 1-22. IEEE Computer Society Press, 2002.
25. E. L. D. E. Todd Austin. SimpleScalar: An Infrastructure for Computer System Modeling. IEEE Computer, pages 59-67, February 2002.
26. S. Toledo. Improving the memory-system performance of sparse-matrix vector multiplication. IMB Journal of Research and Development, 41(6):711-72, 1997.