A low-voltage CMOS 5-bit 600MHz 30mW SAR ADC for UWB wireless receivers

Midwest Symposium on Circuits and Systems

Volumn 2005, Issue , 2005, Pages 187-190

  Sheung, Yan Ng ^a   Jalali, Bahar ^a   Pengbei, Zhang ^a   Wilson, James ^a   Ismail, Mohammad ^a  

^a The Ohio State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA CONVERSION; SUCCESSIVE APPROXIMATION REGISTER ADC (SAR); TIME-INTERLEAVED ARCHITECTURE;

APPROXIMATION THEORY; ELECTRIC POWER UTILIZATION; ITERATIVE METHODS; SIGNAL RECEIVERS; WIRELESS TELECOMMUNICATION SYSTEMS;

CMOS INTEGRATED CIRCUITS;

EID: 33847130615     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSCAS.2005.1594070     Document Type: Conference Paper

References (6)

1. Dieter Draxelmayr, "a 6b 600MHz 10mW ADC Array in Digital 90nm CMOS", 2004 IEEE International Solid-State Circuits Conference
2. Peter Scholtens, Maarten Vertregt, "A 6b 1.6GSample/s Flash ADC in 0.18um CMOS using averaging termination", 2002 International Solid-State Circuits Conference.
3. Chih-Kai Kang, Jia-Yi Chen and Juang-Ying Chueh, "10-bit 10MHz Samples/s 5mW Successive Approximation Register A/D converter", unpublished.
4. David A.Johns and Ken Matrin, "Analog Integrated Circuit Design", JohnWiley & Songs, Inc
5. Jamal, S.M.; Daihong Fu; Chang, N.C.-J.; Hurst, P.J.; Lewis, S.H., "A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration", Solid-State Circuits, IEEE Journal of Volume 37, Issue 12, Dec. 2002 Page(s):1618-1627
6. D. Fu, K. C. Dyer, S. H. Lewis, and P. J. Hurst, "A digital background calibration technique for time-interleaved analog-to-digital converters," IEEE J. Solid-State Circuits, vol. 33, pp. 1904-1911,Dec. 1998.