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Volumn , Issue , 2002, Pages 286-289

A reconfigurable vision system for real-time applications

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; RECONFIGURABLE HARDWARE; SYSTEM-ON-CHIP;

EID: 33847121326     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2002.1188693     Document Type: Conference Paper
Times cited : (4)

References (19)
  • 2
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    • VLSI & Parallel Computing for Pattern Recognition & Artificial Intelligence
    • World Scientific Publishing
    • N. Ranganathan, "VLSI & Parallel Computing for Pattern Recognition & Artificial Intelligence", Series in Machine Perception and Artificial Intelligence, Volume 18, World Scientific Publishing, 1995
    • (1995) Series in Machine Perception and Artificial Intelligence , vol.18
    • Ranganathan, N.1
  • 3
    • 0032141085 scopus 로고    scopus 로고
    • Trends in Embedded Microprocessor Design
    • August
    • Manfred Schelet, "Trends in Embedded Microprocessor Design", IEEE Computer Vol. 31, August 1998, pp. 44-49.
    • (1998) IEEE Computer , vol.31 , pp. 44-49
    • Schelet, M.1
  • 7
    • 0029255778 scopus 로고
    • Real-time Image Processing on a Custom Computing Platform
    • February
    • Peter M. Athanas, and A. Lynn Abbott, "Real-time Image Processing on a Custom Computing Platform", Computer, February 1995, pp. 16-24.
    • (1995) Computer , pp. 16-24
    • Athanas, P.M.1    Abbott, A.L.2
  • 11
    • 85088743972 scopus 로고    scopus 로고
    • Intruction-Level Parallelism for Reconfigurable Computing
    • th International Workshop, Talinn, Estonia, September, Published in Springer Verlag, Hartenstein and Keevallik Eds.
    • th International Workshop, Talinn, Estonia, September 1998, Published in Springer Verlag LNCS 1492, Hartenstein and Keevallik Eds.
    • (1998) LNCS , vol.1492
    • Callahan, T.J.1    Warzynek, J.2
  • 12
    • 0031647478 scopus 로고    scopus 로고
    • A 110-K Transistor 25-Mpixels/s Configurable Image Transform Processor Unit
    • January
    • Stephen Molly, and Rajeev Jain, "A 110-K Transistor 25-Mpixels/s Configurable Image Transform Processor Unit", IEEE Journal of Solid State, Vol. 33, No. 1, January 1998.
    • (1998) IEEE Journal of Solid State , vol.33 , Issue.1
    • Molly, S.1    Jain, R.2
  • 13
    • 84947567597 scopus 로고    scopus 로고
    • Partial Run-Time Reconfiguration Using JRTR
    • R. W. Hartenstein and H. Grunbacher, editors, Field-Programmable Logic and Applications, Springer-Verlag, Berlin, August
    • Scott McMillan and Steven A. Guccione. "Partial Run-Time Reconfiguration Using JRTR". In R. W. Hartenstein and H. Grunbacher, editors, Field-Programmable Logic and Applications, pages 352-360. Springer-Verlag, Berlin, August 2000. Proceedings of the 10th International Workshop on Field-Programmable Logic and Applications, FPL 2000
    • (2000) Proceedings of the 10th International Workshop on Field-Programmable Logic and Applications, FPL 2000 , pp. 352-360
    • McMillan, S.1    Guccione, S.A.2
  • 14
    • 0005703841 scopus 로고    scopus 로고
    • A Reconfigurable computer Primer
    • September
    • Michael Barr, "A Reconfigurable computer Primer", Multimedia Design Systems, September 1998, pag 44-47
    • (1998) Multimedia Design Systems , pp. 44-47
    • Barr, M.1
  • 17
    • 0035056785 scopus 로고    scopus 로고
    • Realtime Field Programmable Gate Array Architecture for Computer Vision
    • January
    • Miguel Arias Estrada, and César Torres Huitzil, "Realtime Field Programmable Gate Array Architecture for Computer Vision", Journal of Electronic Imaging, Volume 10, number 1, January 2001, pp. 289-296
    • (2001) Journal of Electronic Imaging , vol.10 , Issue.1 , pp. 289-296
    • Arias Estrada, M.1    Huitzil, C.T.2
  • 18
    • 4244060382 scopus 로고    scopus 로고
    • An FPGA based Motion Computation Architecture for Real-Time
    • Mexico, D.F. Sept
    • Miguel Arias Estrada, Roberto Garcia de Campo, "An FPGA based Motion Computation Architecture for Real-Time". Visual 2000 conference. Mexico, D.F. Sept. 2000
    • (2000) Visual 2000 Conference
    • Arias Estrada, M.1    Garcia De Campo, R.2
  • 19
    • 35248826992 scopus 로고    scopus 로고
    • Multiple Stereo Matching using an Extended Architecture
    • Ireland. Aug
    • Miguel Arias-Estrada, Juan M. Xicotencatl, "Multiple Stereo Matching using an Extended Architecture", FPL 2001 Belfast, Ireland. Aug. 2001.
    • (2001) FPL 2001 Belfast
    • Arias-Estrada, M.1    Xicotencatl, J.M.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.