Integrated link/CPU voltage scaling for reducing energy consumption of parallel sparse matrix applications

20th International Parallel and Distributed Processing Symposium, IPDPS 2006

Volumn 2006, Issue , 2006, Pages

  Son, Seung Woo ^a   Malkowski, Konrad ^a   Chen, Guilin ^a   Kandemir, Mahmut ^a   Raghavan, Padma ^a  

^a The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER NETWORKS; DATA STORAGE EQUIPMENT; ENERGY UTILIZATION; INTEGRATED CIRCUIT LAYOUT; PROGRAM PROCESSORS; VOLTAGE CONTROL;

FIRST-CLASS OPTIMIZATION METRICES; PARALLEL SPARSE MATRIX APPLICATIONS;

COMPUTER ARCHITECTURE;

EID: 33847115854     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2006.1639596     Document Type: Conference Paper

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