-
1
-
-
33745769262
-
Hot Spot Management in Ultra-low k1 Lithography, 2005
-
K. Hashimoto, S. Usui, S. Nojima, S. Tanaka, E. Yamanaka and S. Inoue, "Hot Spot Management in Ultra-low k1 Lithography", 2005, Proc. International Society for Optical Engineering (SPIE) Symposium on Microlithography, vol. 6156, pp. 1207-1219.
-
Proc. International Society for Optical Engineering (SPIE) Symposium on Microlithography
, vol.6156
, pp. 1207-1219
-
-
Hashimoto, K.1
Usui, S.2
Nojima, S.3
Tanaka, S.4
Yamanaka, E.5
Inoue, S.6
-
2
-
-
0037966005
-
Flexible mask specifications
-
S. Nojima, S. Mimotogi, M. Itoh, O. Ikenaga, S. Hasebe, K. Hashimoto, S. Inoue, M. Goto and I. Mori, "Flexible mask specifications", 2002, Proc. SPIE 22nd Annual BACUS Symposium on Photomask Technology, Vol.4889, pp. 187-196.
-
(2002)
Proc. SPIE 22nd Annual BACUS Symposium on Photomask Technology
, vol.4889
, pp. 187-196
-
-
Nojima, S.1
Mimotogi, S.2
Itoh, M.3
Ikenaga, O.4
Hasebe, S.5
Hashimoto, K.6
Inoue, S.7
Goto, M.8
Mori, I.9
-
4
-
-
0032657144
-
A Systematic Approach to Correct Critical Patterns Induced by the Lithography Process at the Full-Chip Level
-
C.-H. Park, Y.-H. Kim, J.-S. Park, K.-D. Kim, M.-H. Yoo and J.-T. Kong, "A Systematic Approach to Correct Critical Patterns Induced by the Lithography Process at the Full-Chip Level", Proc. International Society for Optical Engineering (SPIE) Symposium on Microlithography, 1999, vol. 3679, pp. 622-629.
-
(1999)
Proc. International Society for Optical Engineering (SPIE) Symposium on Microlithography
, vol.3679
, pp. 622-629
-
-
Park, C.-H.1
Kim, Y.-H.2
Park, J.-S.3
Kim, K.-D.4
Yoo, M.-H.5
Kong, J.-T.6
-
5
-
-
0002428090
-
Full-Chip Process Simulation for Silicon DEC
-
E. Sahouria, Y. Granik, N. Cobb and O. Toublan, "Full-Chip Process Simulation for Silicon DEC", International Conference on Modeling and Simulation of Mircosystems (MSM), 2000, pp. 32-35.
-
(2000)
International Conference on Modeling and Simulation of Mircosystems (MSM)
, pp. 32-35
-
-
Sahouria, E.1
Granik, Y.2
Cobb, N.3
Toublan, O.4
-
6
-
-
2942648580
-
Layout Printability Optimization Using a Silicon Simulation Methodology
-
M. Cote and P. Hurat, "Layout Printability Optimization Using a Silicon Simulation Methodology", 2004, Intl. Symp. on Quality of Electronic Design, pp. 159-164.
-
(2004)
Intl. Symp. on Quality of Electronic Design
, pp. 159-164
-
-
Cote, M.1
Hurat, P.2
-
7
-
-
25144470584
-
Optimized Hardware and Software for Fast, Full Chip Simulation, 2005
-
Y. Cao, Y.-W. Lu, L. Chen and J. Ye, "Optimized Hardware and Software for Fast, Full Chip Simulation", 2005, Proc. International Society for Optical Engineering (SPIE) Symposium on Microlithography, vol. 5754, pp. 407-414.
-
Proc. International Society for Optical Engineering (SPIE) Symposium on Microlithography
, vol.5754
, pp. 407-414
-
-
Cao, Y.1
Lu, Y.-W.2
Chen, L.3
Ye, J.4
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