A new approach to subquadratic space complexity parallel multipliers for extended binary fields

IEEE Transactions on Computers

Volumn 56, Issue 2, 2007, Pages 224-233

  Fan, Haining ^a   Hasan, M Anwar ^a  

^a UNIVERSITY OF WATERLOO   (Canada)

Author keywords

Coordinate transformation; Finite field; Shifted polynomial basis; Subquadratic space complexity multiplier; Toeplitz matrix

Indexed keywords

ALGORITHMS; MATHEMATICAL TRANSFORMATIONS; MATRIX ALGEBRA; POLYNOMIALS; VECTORS;

COORDINATE TRANSFORMATION; FINITE FIELD; RECURSIVE DESIGN ALGORITHM; SUBQUADRATIC SPACE COMPLEXITY MULTIPLIERS; TOEPLITZ MATRIX;

BINARY SEQUENCES;

EID: 33846097630     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2007.19     Document Type: Article

References (37)

1. A. Karatsuba and Y. Ofman, "Multiplication of Multidigit Numbers on Automata," Soviet Physics-Doklady (English translation), vol. 7, no. 7, pp. 595-596, 1963.
2. S. Winograd, Arithmetic Complexity of Computations. SIAM, 1980.
3. m)," IEE Proc.-E, vol. 139, no. 3, pp. 230-236, May 1992.
4. M.A. Hasan and V.K. Bhargava, "Architecture for Low Complexity Rate-Adaptive Reed-Solomon Encoder," IEEE Trans. Computers, vol. 44, no. 7, pp. 938-942, July 1995.
5. m)," Proc. Sixth Int'l Conf. Applied Algebra, Algebraic Algorithms, and Error-Correcting Codes (AAECC-6), pp. 297-309, 1988.
6. B. Sunar and C.K. Koc, "Mastrovito Multiplier for All Trinomials," IEEE Trans. Computers, vol. 48, no. 5, pp. 522-527, May 1999.
7. C.K. Koc and B. Sunar, "Low-Complexity Bit-Parallel Canonical and Normal Basis Multipliers for a Class of Finite Fields," IEEE Trans. Computers, vol. 47, no. 3, pp. 353-356, Mar. 1998.
8. A. Halbutogullari and C.K. Koc, "Mastrovito Multiplier for General Irreducible Polynomials," IEEE Trans. Computers, vol. 49, no. 5, pp. 503-518, May 2000.
9. S.O. Lee, S.W. Jung, C.H. Kim, J. Yoon, J. Koh, and D. Kim, "Design of Bit Parallel Multiplier with Lower Time Complexity," Proc. Sixth Int'l Conf. Information Security and Cryptology (ICICS '03), pp. 127-139, 2003.
10. m)," Proc. Cryptographic Hardware and Embedded Systems (CHES '00), C.K. Koc and C. Paar, eds., pp. 277-292, Aug. 2000.
11. m)," IEEE Trans. Computers, vol. 34, no. 8, pp. 709-717, Aug. 1985.
12. m)," IEEE Trans. Computers, vol. 41, no. 8, pp. 962-971, Aug. 1992.
13. M.A. Hasan, M.Z. Wang, and V.K. Bhargava, "A Modified Massey-Omura Parallel Multiplier for a Class of Finite Fields," IEEE Trans. Computers, vol. 42, no. 10, pp. 1278-1280, Oct. 1993.
14. m)," IEEE Trans. Computers, vol. 51, no. 5, pp. 511-520, May 2002.
15. m) Yielding Small Complexity Arithmetic Circuits," IEEE Trans. Computers, vol. 47, no. 9, pp. 938-946, Sept. 1998.
16. R. Katti and J. Brennan, "Low Complexity Multiplication in Finite Field Using Ring Representation," IEEE Trans. Computers, vol. 52, no. 4, pp. 418-427, Apr. 2003.
17. C. Negre, "Quadrinomial Modular Arithmetic Using Modified Polynomial Basis," Proc. Int'l Conf. Information Technology: Coding and Computing (ITCC '05), vol. 1, pp. 550-555, 2005.
18. m) Multiplication and Division over the Dual Basis," IEEE Trans. Computers, vol. 45, no. 3, pp. 319-327, Mar. 1996.
19. H. Wu, M.A. Hasan, and I.F. Blake, "New Low-Complexity Bit-Parallel Finite Field Multipliers Using Weakly Dual Bases," IEEE Trans. Computers, vol. 47, no. 11, pp. 1223-1234, Nov. 1998.
20. n) Multiplier for All Trinomials," IEEE Trans. Computers, vol. 54, no. 4, pp. 485-490, Apr. 2005.
21. C. Paar, "A New Architecture for a Parallel Finite Field Multiplier with Low Complexity Based on Composite Fields," IEEE Trans. Computers, vol. 45, no. 7, pp. 856-861, July 1996.
22. 4n)," IEEE Trans. Computers, vol. 47, no. 2, pp. 162-170, Feb. 1998.
23. n)," Proc. Cryptographic Hardware and Embedded Systems (CHES '02), pp. 381-399, 2003.
24. n)," Proc. IEEE Workshop Heterogeneous Reconfigurable Systems on Chip, 2002.
25. 33) Multipliers," Proc. Int'l Symp. Circuits and Systems (ISCAS '03), vol. II, pp. 268-271, 2003.
26. A. Weimerskirch and C. Paar, "Generalizations of the Karatsuba Algorithm for Efficient Implementations," http:// www.crypto.ruhr-uni-bochum.de/imperia/md/content/texte/kaweb.pdf, 2003.
27. m)," Proc. Int'l Conf. Computer Science and Technology (CST '03), pp. 405-410, 2003.
28. m)," Proc. 13th Asilomar Conf. Signals, Systems, and Computers, vol. 1, pp. 471-477, Nov. 2004.
29. n)," Proc. 23rd Biennial Symp. Comm., 2006.
30. 2," Proc. 12th Workshop Selected Areas in Cryptography (SAC '05), 2005.
31. k) Multipliers," IEEE Trans. Computers, vol. 53, no. 9, pp. 1097-1105, Sept. 2004.
32. k) Using Trinomial Residue Arithmetic," Proc. 17th IEEE Symp. Computer Arithmetic (ARITH '05), 2005.
33. D.J. Bernstein, "Multidigit Multiplication for Mathematicians," Advances in Applied Math., to appear.
34. G. Seroussi, "Table of Low-Weight Binary Irreducible Polynomials," Technical Report HPL-98-135, Hewlett-Packard Laboratories, Palo Alto, Calif., http://www.hpl.hp.com/techreports/ 98/HPL-98-135.html, Aug. 1998.
35. P.L. Montgomery, "Five, Six, and Seven-Term Karatsuba-Like Formulae," IEEE Trans. Computers, vol. 54, no. 3, pp. 362-369, Mar. 2005.
36. n)," IEEE Trans. Circuits and Systems-I: Regular Papers, accepted.
37. n) Multiplication," Technical Report CACR 2006-13, Univ. of Waterloo, Waterloo, Canada, May 2006.