Design of Bit Parallel Multiplier with Lower Time Complexity

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2971, Issue , 2004, Pages 127-138

  Lee, Seon Ok ^a   Jung, Seok Won ^a   Kirn, Chang Han ^b   Yoon, Janghong ^c   Koh, Jae Young ^c   Kim, Daeho ^c  

^a Korea University   (South Korea)

^b Semyung University   (South Korea)

^c National Security Research Institute (NSRI)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

SECURITY OF DATA;

ARITHMETIC OPERATIONS; BIT-PARALLEL MULTIPLIERS; CRITICAL OPERATIONS; EFFICIENT IMPLEMENTATION; FINITE FIELD OPERATIONS; PROPOSED ARCHITECTURES; SPACE COMPLEXITY; TIME COMPLEXITY;

RECONFIGURABLE HARDWARE;

EID: 35048817521     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-24691-6_11     Document Type: Article

References (14)

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