New low-complexity bit-parallel finite field multipliers using weakly dual bases

IEEE Transactions on Computers

Volumn 47, Issue 11, 1998, Pages 1223-1234

  Wu, Huapeng ^a,b   Hasan, M Anwarul ^a,b   Blake, Ian F ^a,c  

^a IEEE   (Canada)

^b UNIVERSITY OF WATERLOO   (Canada)

^c HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

Bit parallel multiplier; Finite field arithmetic; Irreducible polynomials; Trinomials; Weakly dual basis

Indexed keywords

BINARY CODES; COMPUTATIONAL COMPLEXITY; DIGITAL ARITHMETIC; POLYNOMIALS;

BIT PARALLEL MULTIPLIERS;

MULTIPLYING CIRCUITS;

EID: 0032206245     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.736433     Document Type: Article

References (23)

1. H. Wu, M.A. Hasan, and I.F. Blake, "Low Complexity Bit-Parallel Finite Field Multipliers," Proc. Fifth Canadian Workshop Information Theory, pp. 109-112, Toronto, Ontario, 3-6 June 1997.
2. R. Lidl and H. Niederreiter, Finite Fields. Reading, Mass.: Addison-Wesley, 1983.
3. I.S. Hsu, T.K. Truong, L.J. Deutsch, and J.S. Reed, "A Comparison of VLSI Architecture of Finite Fields Multipliers Using Dual, Normal, or Standard Bases," IEEE Trans. Computers, vol. 37, no. 6, pp. 735-39, June 1988.
4. T.C. Bartee and D.I. Schneider, "Computation with Finite Fields," Information and Computing, vol. 6, pp. 79-98, Mar. 1963.
5. E.R. Berlekamp, Algebraic Coding Theory. New York: McGraw-Hill, 1968.
6. m)," IEEE Trans. Computers, vol. 20, no. 12, pp. 1,573-1,578, Dec. 1971.
7. m)," IEEE Trans. Computers, vol. 33, no. 4, pp. 357-360, Apr. 1984.
8. m)," IEEE J. Selected Areas in Comm., vol. 4, no. 1, pp. 62-66, Jan. 1986.
9. E.D. Mastrovito, "VLSI Architectures for Computations in Galois Fields," PhD dissertation, Linköping Univ., Linköping, Sweden, 1991.
10. m)," Information and Computing, vol. 83, pp. 21-40, 1989.
11. m)," IEEE Trans Computers, vol. 41, no. 8, pp. 962-971, Aug. 1992.
12. C. Paar, "Efficient VLSI Architectures for Bit-parallel Computation in Galois Fields," PhD dissertation, Informatik Kommunikationstechnik, VDI-Verlag, Düsseldorf, 1994.
13. J.L. Massey and J.K. Omura, "Computational Method and Apparatus for Finite Field Arithmetic," U.S. patent no. 4,587,627, 1986.
14. M.A. Hasan, M. Wang, and V.K. Bhargava, "A Modified Massey-Omura Parallel Multiplier for a Class of Finite Fields," IEEE Trans. Computers, vol. 42, no. 8, pp. 1,278-1,280, Oct. 1993.
15. E.R. Berlekamp, "Bit-Serial Reed-Solomon Encoders," IEEE Trans. Information Theory, vol. 28, pp. 869-974, 1982.
16. M. Morii, M. Kasahara, and D.L. Whiting, "Efficient Bit-Serial Multiplication and Discrete-Time Wiener-Hoph Equation Over Finite Fields," IEEE Trans. Information Theory, vol. 35, pp. 1,177-1,184, 1989.
17. M. Wang and I.F. Blake, "Bit Serial Multiplication in Finite Fields," SIAM Discrete Math., vol. 3, no. 1, pp. 140-148, Feb. 1990.
18. C.C. Wang, "An Algorithm to Design Finite Field Multipliers Using a Self-Dual Normal Basis," IEEE Trans. Computers, vol. 38, no. 10, pp. 1,457-1,459, Oct. 1989.
19. m) Multiplication and Division Over the Dual Basis," IEEE Trans. Computers, vol. 45, no. 3, pp. 319-327, Mar. 1996.
20. qn," Designs, Codes, and Cryptography, vol. 3, pp. 333-345, 1993.
21. I.F. Blake, S. Gao, and R. Lambert, "Constructive Problems for Irreducible Polynomials Over Finite Fields," Proc. Canadian Workshop Information Theory, pp. 1-23, 1993.
22. S.D. Cohen, "On Irreducible Polynomials of Certain Types in Finite Fields," Proc. Cambridge Philosophical Sec., vol. 66, pp. 335-344, 1969.
23. H. Wu and M.A. Hasan, "Low Complexity Bit-parallel Multipliers for a Class of Finite Fields," IEEE Trans. Computers, vol. 47, no. 8, pp. 883-887, Aug. 1998.