Long retention of gain-cell dynamic random access memory with undoped memory node

IEEE Electron Device Letters

Volumn 28, Issue 1, 2007, Pages 48-50

  Nishiguchi, Katsuhiko ^a   Fujiwara, Akira ^a   Ono, Yukinori ^a   Inokawa, Hiroshi ^a   Takahashi, Yasuo ^a  

^a Kashino Diverse Brain Research Laboratory of NTT Communication Science Laboratories   (Japan)

Author keywords

Gain cell dynamic random access memory (DRAM); Long data retention; Two layered gate; Undoped silicon on insulator (SOI) MOSFET

Indexed keywords

GATES (TRANSISTOR); JUNCTION GATE FIELD EFFECT TRANSISTORS; LEAKAGE CURRENTS; MOSFET DEVICES; POLYSILICON; SILICON ON INSULATOR TECHNOLOGY;

GAIN-CELL DYNAMIC RANDOM ACCESS MEMORY (DRAM); LONG DATA RETENTION; TWO-LAYERED GATE; UNDOPED SILICON-ON-INSULATOR (SOI) MOSFET;

RANDOM ACCESS STORAGE;

EID: 33845968070     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2006.887625     Document Type: Article

References (8)

1. S. Shukuri, T. Kure, and T. Nishida, "A complementary gain cell technology for Sub-1V supply DRAMs," in IEDM Tech. Dig., 1992, pp. 1006-1007.
2. N. Ikeda, T. Terano, H. Moriya, T. Emori, and T. Kobayashi, "A novel logic compatible gain cell with two transistor and one capacitor," in VLSI Symp. Tech. Dig., 2000, pp. 168-169.
3. T. Nishihara, N. Ikeda, H. Aozawa, Y. Miyazawa, and A. Ochiai, "A buried capacitor DRAM cell with bonded SOI for 256 M and 1 Gbit DRAMs," in IEDM Tech. Dig., 1992, pp. 803-806.
4. Y. Takahashi, A. Fujiwara, K. Yamazaki, H. Namatsu, K. Kurihara, and K. Murase, "A Si memory device composed of a one-dimensional metal-oxide-semiconductor field-effect-transistor switch and a single-electron-transistor detector," Jpn. J. Appl. Phys. Lett., vol. 38, no. 4B, pp. 2457-2461, Apr. 1999.
5. A. Wei and D. A. Antoniadis, "Measurement of transient effects in SOI DRAM/SRAM access transistors," IEEE Electron Device Lett., vol. 17, no. 5, pp. 193-195, May 1996.
6. F. Morishia, K. Suma, M. Hirose, T. Tsuruda, Y. Yamaguchi, T. Eimori, T. Oashi, K. Arimoto, Y. Inoue, and T. Nishimura, "Leakage mechanism due to floating body and countermeasure on dynamic retention mode of SOI-DRAM," in VLSI Symp. Tech. Dig., 1994, pp. 141-142.
7. T. Nishihara, H. Moriya, N. Ikeda, H. Aozawa, and Y. Miyazawa, "Data retention in ultra-thin-film-SOI DRAM with buried capacitor cell," in VLSI Symp. Tech. Dig., 1994, pp. 39-40.
8. N. J. Stone and H. Ahmed, "A memory cell with single-electron and metal-oxide-semiconductor transistor integration," Appl. Phys. Lett., vol. 74, no. 9, pp. 1293-1295, Mar. 1999.