A memory cell with single-electron and metal-oxide-semiconductor transistor integration

Applied Physics Letters

Volumn 74, Issue 9, 1999, Pages 1293-1295

  Durrani, Zahid A K ^a   Irvine, Andrew C ^a   Ahmed, Haroon ^a   Nakazato, Kazuo ^b  

^a UNIVERSITY OF CAMBRIDGE   (United Kingdom)

^b HITACHI CAMBRIDGE LABORATORY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; ELECTRONS; HIGH TEMPERATURE OPERATIONS; HYSTERESIS; MOSFET DEVICES; OSCILLATIONS; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON ON INSULATOR TECHNOLOGY; TUNNEL JUNCTIONS;

COULOMB GAP; MEMORY CELL; MEMORY NODE; SINGLE ELECTRON TRANSISTOR;

SEMICONDUCTOR DEVICE STRUCTURES;

EID: 0033095276     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.123528     Document Type: Article

References (6)

1. K. Yano, T. Ishii, T. Hashimoto, T. Kobayashi, F. Murai, and K. Seki, Tech. Dig. Int. Electron Devices Meet. 93, 541 (1993).
2. S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe, and K. Chan, Appl. Phys. Lett. 68, 1377 (1996).
3. A. Nakajima, T. Futatsugi, K. Kosemura, T. Fukano, and N. Yokoyama, Appl. Phys. Lett. 70, 1742 (1997).
4. N. J. Stone and H. Ahmed, Appl. Phys. Lett. 73, 2134 (1998).
5. H. Mizuta, D. Williams, K. Katayama, H-O. Müllier, K. Nakazato, and H. Ahmed, Proceedings of Second International Workshop on Physics and Modeling of Devices Based on Low-dimensional Structures, Aizu-Wakamatsu, Japan, March 12/13 1998.
6. R. A. Smith and H. Ahmed, J. Appl. Phys. 81, 2699 (1997).