Design exploration with imprecise latency and register constraints

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 12, 2006, Pages 2650-2662

  Chantrapornchai, Chantana ^b   Surakampontorn, Wanlop ^a,c   Sha, Edwin Hsing Mean ^a,d  

^a IEEE

^b SILPAKORN UNIVERSITY   (Thailand)

^c KING MONGKUT'S UNIVERSITY OF TECHNOLOGY THONBURI   (Thailand)

^d The University of Texas at Dallas   (United States)

Author keywords

Imprecise design exploration; Imprecise information; Inclusion scheduling (IS); Multiple design attributes; Register constraint; Scheduling allocation

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; FOURIER TRANSFORMS; ITERATIVE METHODS; SCHEDULING; SPECIFICATIONS;

IMPRECISE DESIGN EXPLORATION; IMPRECISE INFORMATION; INCLUSION SCHEDULING (IS); MULTIPLE DESIGN ATTRIBUTES; REGISTER CONSTRAINT;

INTEGRATED CIRCUIT LAYOUT;

EID: 33845681208     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2006.882591     Document Type: Article

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