Timing-driven routing for FPGAs based on Lagrangian relaxation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 4, 2003, Pages 506-511

  Lee, Seokjin ^a   Wong, Martin D F ^b  

^a The University of Texas at Austin   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

Field programmable gate arrays; Lagrangian relaxation; Timing driven routing

Indexed keywords

ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS; FLIP FLOP CIRCUITS; GRAPH THEORY; ITERATIVE METHODS; LAGRANGE MULTIPLIERS; MATHEMATICAL PROGRAMMING; TABLE LOOKUP;

CRITICAL PATH DELAY; LAGRANGIAN RELAXATION; TIMING-DRIVEN ROUTING;

LOGIC DESIGN;

EID: 0037389313     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.809645     Document Type: Article

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