메뉴 건너뛰기




Volumn 2006, Issue , 2006, Pages 1208-1212

Parametric thermal modeling of 3D stacked chip electronics with interleaved solid heat spreaders

Author keywords

Heat conduction; IC; Integrated circuit; Simulation; Thermal management; Three dimensional

Indexed keywords

POWER DISSIPATIONS; SOLID HEAT SPREADERS; STACKED CHIPS;

EID: 33845585321     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ITHERM.2006.1645482     Document Type: Conference Paper
Times cited : (13)

References (6)
  • 2
    • 0034452632 scopus 로고    scopus 로고
    • Full chip thermal analysis of planar (2-D) and vertically integrated (3-D) high performance ICs
    • Sungjun Im and Kaustav Banerjee, "Full Chip Thermal Analysis of Planar (2-D) and Vertically Integrated (3-D) High Performance ICs," International Electron Devices Meeting 2000 Technical Digest, pp. 727-30, 2000.
    • (2000) International Electron Devices Meeting 2000 Technical Digest , pp. 727-730
    • Sungjun, I.1    Banerjee, K.2
  • 5
    • 27744591783 scopus 로고    scopus 로고
    • Self-consistent modeling of heating and MOSFET performance in 3-D integrated circuits
    • Nov.
    • A. Akturk, N. Goldsman, and G. Metze, "Self-consistent modeling of heating and MOSFET performance in 3-D integrated circuits," IEEE Transactions on Electron Devices, vol. 52, no. 11, pp. 2395-2403, Nov. 2005.
    • (2005) IEEE Transactions on Electron Devices , vol.52 , Issue.11 , pp. 2395-2403
    • Akturk, A.1    Goldsman, N.2    Metze, G.3
  • 6
    • 0347409236 scopus 로고    scopus 로고
    • Efficient thermal placement of standard cells in 3D ICs using a force directed approach
    • B. Goplen and S. Sapatnekar, "Efficient thermal placement of standard cells in 3D ICs using a force directed approach" International Conference on Computer Aided Design , pp. 86-89, 2003.
    • (2003) International Conference on Computer Aided Design , pp. 86-89
    • Goplen, B.1    Sapatnekar, S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.