Design optimization for isolation in high wiring density packages with high speed SerDes links

Proceedings - Electronic Components and Technology Conference

Volumn 2006, Issue , 2006, Pages 187-193

  Na, Nju ^a   Audet, Jean ^b   Shan, Lei ^c   Cranmer, Michael ^a   Lafontant, Gary ^a   Zwitter, Deborah ^a  

^a IBM   (United States)

^b IBM CANADA LTD   (Canada)

^c IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL CAPACITY; COST EFFECTIVENESS; ELECTRIC WIRING; INTEGRATED CIRCUIT LAYOUT; LAMINATING; OPTIMIZATION;

CHANNEL PERFORMANCE; COST OPTIMIZATION; DENSITY PACKAGES; LAMINATE PACKAGES;

CHIP SCALE PACKAGES;

EID: 33845584361     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2006.1645646     Document Type: Conference Paper

References (4)

1. Tingdong Zhou and George A Katopis, "Application of Closed-form Wiring Escpe Formulae to a High Performance Printed Wiring Board", IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, Prinston, New Jersey, Oct. 27-29, 2003, pp. 225-228.
2. th Electronic Components and Technology Conference, June 1-4, 2004, pp. 1776-1783.
3. Nanju Na, Jean Audet and Deborah Zwitter, "Discontinuity impacts and design considerations of high speed differential signals in FC-PBGA packages with high wiring density", IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, Austin, Texas, Oct. 24-26, 2005, pp. 107-110.
4. Jean Audet and Nanju Na, Flip Chip Ball Grid Array Pacakge Electrical to Physical Design Implementation Guide for Cu08 Packaging, IBM propriety, 2005.