Discontinuity impacts and design considerations of high speed differential signals in FC-PBGA packages with high wiring density

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn 2005, Issue , 2005, Pages 107-110

  Na, Nju ^a   Auder, Jean ^b   Zwitter, Deborah ^a  

^a IBM   (United States)

^b IBM CANADA LTD   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; PARAMETER ESTIMATION; SIGNAL PROCESSING; SPURIOUS SIGNAL NOISE; WAVEFORM ANALYSIS;

FC PBGA PACKAGES; HIGH WIRING DENSITY; OPTIMAL PERFORMANCE;

ELECTRONICS PACKAGING;

EID: 33845595076     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEP.2005.1563713     Document Type: Conference Paper

References (6)

1. D. N. de Araujo, J. Diepenbrock, M. Cases, N. Pham, "Transmitter and Channel Equalization for High Speed Server Interconnects", Electrical Performance of Electronic Packaging, pp. 221-224, Oct. 2003.
2. High Speed SerDes Chip Packaging Electrical Requirements for CuO8, IBM SA15-5828-00.
3. Moses Cases, D. N. de Araujo, E. Blackshear, "Laminate Package Trends for High Speed System Interconnects", Electrical Performance of Electronic Packaging, pp. 147-150, Oct. 2003.
4. Lei Shan, Young Kwark, Daniel Dreps and Jean Trewhella, "How Detrimental Could a Via Be?", Electrical Performance of Electronic Packaging, pp. 91-94, Oct. 2004.
5. Jean Audet, Nanju Na, "FCPBGA Design Analysis for CuO8 Packaging", White paper, IBM System and Technology Group, 2005.
6. FCPBGA Electrical to Physical Design Guide for CuO8 Packaging, IBM System and Technology Group, 2005.