Applications of closed-form wiring escape formulae to a high performance printed wiring board

Electrical Performance of Electronic Packaging

Volumn , Issue , 2003, Pages 225-228

  Zhou, Tingdong ^a   Katopis, George A ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS PACKAGING;

CLOSED FORM; CLOSED-FORM FORMULAE; PACKAGE LEVELS; VIA TECHNOLOGIES;

PRINTED CIRCUIT BOARDS;

EID: 33845563058     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEP.2003.1250037     Document Type: Conference Paper

References (4)

1. Peter Sandborn, and Hector Moreno, "Conceptual design of multi-chip modules and systems, " Kluwer academic publishers, 1994.
2. Joel Darnauer, and Wayne Dai, "Fast pad redistribution from periphery-IO to area-IO" 1994 IEEE Multi-Chip Module Conference, pp 38-43, Santa Cruz, CA, USA, March 15-17, 1994.
3. Michio Horiuchi, Eiji Yoda, and Yukiharu Takeuchi, "Escape routing design to reduce the number of layers in area array packaging, " IEEE transactions on advanced packaging, vol. 23, no. 4, November, 2000.
4. George Katopis, and Tingdong Zhou, "Applications of Wiring Escape Estimation, " The 7th IEEE Workshop on Signal Propagation on Interconnects, pp 123-126, Siena, Italy, May 11-14, 2003.