Systematic evaluation of die thinning application in a power SIP by simulation

Proceedings - Electronic Components and Technology Conference

Volumn 2006, Issue , 2006, Pages 981-989

  Yong, Liu ^a   Desbiens, Don ^a   Irving, Scott ^a   Luk, Timwah ^a   Lolar, Carl ^a   Yumin, Liu ^b   Qiuxiao, Qian ^b  

^a FAIRCHILD SEMICONDUCTOR   (United States)

^b Fairchild Semiconductor   (China)

Author keywords

[No Author keywords available]

Indexed keywords

POWER COMPONENTS; SYSTEM IN PACKAGE (SIP); THINNING DIES; ULTRA THIN DIE;

COMPUTER SIMULATION; DIE CASTING; FINITE ELEMENT METHOD; INTEGRATED CIRCUITS; RELIABILITY THEORY; SEMICONDUCTOR DIODES; THERMAL CYCLING;

CHIP SCALE PACKAGES;

EID: 33845580299     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2006.1645773     Document Type: Conference Paper

References (9)

1. Wetz, L., White, J., and Keser, B., "Improvement in WL-CSP Reliability by Wafer Thinning", Proceedings of 53th Electronic Components and Technology Conference, New Orleans, May2003.
2. Reiche, M. and Wagner, G., "Wafer Thinning-Techniques for Ultra-thin Wafers," Advanced Packaging, March2003.
3. Timoshenko, S. and Woinowsky-Krieger, S., "Theory of Plates and Shells," McGraw-Hill, 1959
4. Wu, E., "Influence of Grinding Process on Semiconductor Chip Strength", Proceedings of 53th Electronic Components and Technology Conference, 2002.
5. Tummala, R. R., et al., "Fundamentals of Microsystems Packaging", McGraw-Hill, 2001
6. ANSYS®/Ls-dyna User's Manual, V10, October, 2005.
7. King, J. A., "Materials Handbook for Hybrid Microelectronics", Artech House, 1988.
8. "Silicon Properties", Engineering Design Research Laboratory, California Institute of Technology, 2000
9. SPM3 die strength test report, Fairchild-ZUT Joint Lab, 2006.