Improvement in WL-CSP reliability by wafer thinning

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2003, Pages 853-856

  Wetz, Li ^a   White, Jerry ^a   Keser, Beth ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; COSTS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; OPTIMIZATION; PLASMA ETCHING; RELIABILITY; SILICON WAFERS; SOLDERING; SPATIAL VARIABLES CONTROL;

BOARD LEVEL RELIABILITY; BONDPADS; REDISTRIBUTED METAL BONDPADS; SOLDER BALLS; WAFER BACKGRINDING; WAFER LEVEL CHIP SCALE PACKAGING; WAFER THINNING;

ELECTRONICS PACKAGING;

EID: 0038012492     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. L. Wetz, B. Keser, J. White, "Design and Reliability of a New WL-CSP," Proceedings of IMAPS 2002, Denver, CO, September 2002, pp. 211-215.
2. S. Savastiouk, O. Siniaguine, E. Korczynski, "3-D Stacked Wafer-Level Packaging," Advanced Packaging, March 2000.
3. E. Gaulhofer, H. Oyrer, "Wafer Thinning and Strength Enhancement to Meet Emerging Packaging Requirements," IEMT Europe 2000 Symposium, Semicon, Munich Germany, April 2000.
4. O. Siniaguine, "Atmospheric Downstream Plasma Etching of Si Wafers," 23rd IEEE/CPTM International Electronics Manufacturing Technology Symposium, Austin, TX, October 1998.
5. D. Bursky, "Thin Is In: Wafer-Thinning Method Delivers Ultra-Slim Chips with a Clean Process," Electronic Design, Vol. 47, No. 18 (1999).
6. B. Keser, R. Bajaj, T. Fang, "Redistribution and Bumping of a High I/O Device for Flip Chip Assembly," IEEE Trans. on Adv. Packaging, 23 (1) p. 3, 2000.