Bed of nails: Fine pitch wafer-level packaging interconnects for high performance nano devices

Proceedings of 7th Electronics Packaging Technology Conference, EPTC 2005

Volumn 2, Issue , 2005, Pages 658-663

  Rao, Vempati Srinivasa ^a,b   Kripesh, V ^a   Yoon, Seung Wook ^a   Witarsa, David ^a   Tay, A A O ^b  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ASPECT RATIO; ELECTRIC POWER SYSTEM INTERCONNECTION; INTEGRATED CIRCUITS; NANOSTRUCTURED MATERIALS; SILICON WAFERS; THERMAL CYCLING;

DISTANCE FROM NEUTRAL POINT (DNP); SOLDER BUMPING; SUBSTRATE INTERCONNECTION;

ELECTRONICS PACKAGING;

EID: 33845565139     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. International Technology Roadmap for Semiconductors (2003)- Assembly and Packaging. [Online]. Available: http//piblic.itrs.net
2. R. Rao. Tummala, "Fundamentals of Microsystems Packaging," New York: McGrow-Hill, 2001.
3. Darrel R. Frear, "Materials issues in area-arry microelectronic packaging," JOM, 51(3), 1999, pp.22-27.
4. Donald L. Smith et. al, "Flip-Chip Bonding on 6-μm Pitch using Thin-film Microspring Technology," in proc. Electronic Components and Technology Conf., 1998, pp. 325-329.
5. M. Bakir et. al, "Sea of Leads ultra-high density compliant wafer level packaging technology," Proceedings of 2002 Electronic Components and Technology Conference, pp. 1087-1094.
6. Vempati Srinivasa Rao et. al, "Bed of Nails - 100 microns pitch wafer level interconnections process," Proceedings of 2004 Electronics Packaging Technology Conference, pp. 444.