Investigation of residual stress in wafer level interconnect structures induced by wafer processing

Proceedings - Electronic Components and Technology Conference

Volumn 2006, Issue , 2006, Pages 344-349

  Guotao, Wang ^a,c   Dongwen, Gan ^a   Groothuis, Steven ^b   Ho, Paul S ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b MICRON TECHNOLOGY INC   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIRTH AND DEATH TECHNIQUES; DAMASCENE STRUCTURES; WAFER PROCESSING;

COMPUTER SIMULATION; COPPER; FINITE ELEMENT METHOD; MATHEMATICAL MODELS; RESIDUAL STRESSES; X RAY ANALYSIS;

WSI CIRCUITS;

EID: 33845562910     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2006.1645669     Document Type: Conference Paper

References (7)

1. E. T. Ogawa, K. -D. Lee, H. Matsuhashi, K. - S. Ko, P. R. Justison, A. N. Ramamurthi, A. J. Bierwag, P. S. Ho, V. A. Blaschke and R. H. Havemann, "Statistics of Electromigration Early Failures in Cu/Oxide Dual-Damascene Interconnects", 2001 IEEE International Reliability Physics Symposium Proceedings 39th Annual, 2001, pp. 341-349
2. th Annual, 2002, pp. 322-326
3. T. D. Sullivan, "Stress-induced Voiding in Microelectronic Metallization: Void Growth Models and Refinements", in Annual Reviews in Materials Science, 26, 1996, pp. 333-364
4. th Annual, 2001, pp. 334-340
5. R.-M. Keller, S.P. Baker and E.Artz, "Stress-Temperature Behavior of Unpassivated Thin Copper Films", Acta Mater., vol. 47, no.2, 1999, pp.415-426
6. ANSYS manual
7. E. T. Ogawa, J. W. McPherson, J. A. Rosal, K. J. Dickerson, T. -C. Chiu, L. Y. Tsung, M. K. Jain, T. D. Bonifield, J. C. Ondrusek and W. R. McKee, "Stress-Induced Voiding Under Vias Connected To Wide Cu Metal Leads", 2002 IEEE International Reliability Physics Symposium Proceedings 40th Annual, 2002, pp. 312-321