Chip-level performance improvement using triple damascene wiring design concept for the 0.13 μm CMOS generation and beyond

IEICE Transactions on Electronics

Volumn E89-C, Issue 11, 2006, Pages 1544-1550

  Oda, Noriaki ^a   Kunishima, Hiroyuki ^a   Kyouno, Takashi ^a   Takeda, Kazuhiro ^a   Tanaka, Tomoaki ^a   Takewaki, Toshiyuki ^a   Ikeda, Masahiro ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

CMOS; Copper; Damascene; Design

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC WIRING; LOGIC DESIGN; MASKS; PROGRAM PROCESSORS;

DAMASCENE; GRAPHIC MPU CHIPS; MULTI-PROCESSING UNIT (MPU); WIRING DESIGN;

MICROPROCESSOR CHIPS;

EID: 33845562250     PISSN: 09168524     EISSN: 17451353     Source Type: Journal    
DOI: 10.1093/ietele/e89-c.11.1544     Document Type: Article

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