Enhancing drop test efficacy for product quality improvement through interconnection shear tests

Proceedings - Electronic Components and Technology Conference

Volumn 2006, Issue , 2006, Pages 72-77

  Hanabe, Murali ^a   Canumalla, Sridhar ^a   Kujala, Arni ^a  

^a NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DROP TESTS; FAILURE MECHANISMS; HIGH SPEED SHEAR;

CORRELATION METHODS; FAILURE (MECHANICAL); INTEGRATED CIRCUIT LAYOUT; QUALITY ASSURANCE; SHEAR STRENGTH;

CHIP SCALE PACKAGES;

EID: 33845561924     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2006.1645628     Document Type: Conference Paper

References (5)

1. rd Electronic Components and Technology Conference, 2003, pp 105-112.
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3. A. Bansal, S. Yoon, J. Xie, Y. Li and V. Mahadev, "Comparison of substrate finishes for flip chip packages," Proceedings of the 55th Electronic Components and Technology Conference, 2005, pp 30-37.
4. E. H. Wong, R. Rajoo, Y. W. Mai, S. K. W. Seah, K. T. Tsai and L. M. Yap, "Drop Impact: Fundamentals & impact characterization of solder joints", Proceedings of the 55th Electronic Components and Technology Conference, 2005, pp 1202-1209.
5. M. Hanabe and S. Canumalla, "Package to board interconnection shear strength (PBISS) behavior at high strain rates approaching mechanical drop", Proceedings of the 54th Electronic Components and Technology Conference, 2004, pp 1263-1270.