Package to board interconnection shear strength (PBISS): Effect of surface finish, PWB build-up layer and chip scale package structure

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2003, Pages 105-112

  Canumalla, Sridhar ^a   Yang, Hee Dong ^a   Viswanadham, Puligandla ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CORROSION PREVENTION; PRINTED CIRCUIT BOARDS; SEMICONDUCTOR DEVICE STRUCTURES; SHEAR STRESS; SOLDERING; SURFACE TESTING;

CHIP SCALE PACKAGE STRUCTURE; ORGANIC SOLDERABILITY PRESERVATIVE; PACKAGE TO BOARD INTERCONNECTION SHEAR STRENGTH; SURFACE FINISH;

CHIP SCALE PACKAGES;

EID: 0038690046     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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10. S.Canumalla, Patent pending.
11. T. Reinikainen and S. Canumalla, unpublished work.