-
1
-
-
33845320645
-
-
Technical Report 06-020, Computer Science, U. of Minnesota
-
Das, A., Fu, R., Zhai, A., Hsu, W.-C.: Issues and Support for Dynamic Register Allocation. Technical Report 06-020, Computer Science, U. of Minnesota, 2006
-
(2006)
Issues and Support for Dynamic Register Allocation
-
-
Das, A.1
Fu, R.2
Zhai, A.3
Hsu, W.-C.4
-
2
-
-
33749382556
-
Dynamic helper-threaded prefetching for sun UltraSPARC processors
-
Lu, J., Das, A., Hsu, W-C., Nguyen, K., Abraham, S.: Dynamic Helper-threaded Prefetching for Sun UltraSPARC Processors. MICRO 2005.
-
MICRO 2005
-
-
Lu, J.1
Das, A.2
Hsu, W.-C.3
Nguyen, K.4
Abraham, S.5
-
3
-
-
67650020024
-
The performance of runtime data cache prefetching in a dynamic optimization system
-
Jiwei Lu, Howard Chen, Rao Fu, Wei-Chung Hsu, Bobbie Othmer, Pen-Chung Yew: The Performance of Runtime Data Cache Prefetching in a Dynamic Optimization System. MICRO 2003.
-
MICRO 2003
-
-
Lu, J.1
Chen, H.2
Fu, R.3
Hsu, W.-C.4
Othmer, B.5
Yew, P.-C.6
-
4
-
-
2942729643
-
Design and implementation of a lightweight dynamic optimization system
-
Jiwei Lu, Howard Chen, Pen-Chung Yew, Wei Chung Hsu: Design and Implementation of a Lightweight Dynamic Optimization System. Journal of Instruction-Level Parallelism, Volume 6, 2004
-
(2004)
Journal of Instruction-level Parallelism
, vol.6
-
-
Lu, J.1
Chen, H.2
Yew, P.-C.3
Hsu, W.C.4
-
5
-
-
3042613777
-
Ispike: A post-link optimizer for the IntelItaniumArchitecture
-
Chi-Keung Luk, Robert Muth, Harish Patil, Robert Cohn, Geoff Lowney: Ispike: A Post-link Optimizer for the IntelItaniumArchitecture. CGO, 2004.
-
(2004)
CGO
-
-
Luk, C.-K.1
Muth, R.2
Patil, H.3
Cohn, R.4
Lowney, G.5
-
7
-
-
0030697710
-
Goodwin: Interprocedural dataflow analysis in an executable optimizer
-
David W. Goodwin: Interprocedural dataflow analysis in an executable optimizer. PLDI, 1997
-
(1997)
PLDI
-
-
David, W.1
-
9
-
-
0028424965
-
Shade: A fast instruction-set simulator for execution profiling
-
May. 1994
-
Cmelik, B. and Keppel, D. 1994: Shade: a fast instruction-set simulator for execution profiling. SIGMETRICS Perform. Eval. Rev. 22, 1 (May. 1994), 128-137.
-
(1994)
SIGMETRICS Perform. Eval. Rev.
, vol.22
, Issue.1
, pp. 128-137
-
-
Cmelik, B.1
Keppel, D.2
-
11
-
-
0034449842
-
Dynamo: A transparent dynamic optimization system
-
Bala, V., Duesterwald, E., and Banerjia, S: Dynamo: a transparent dynamic optimization system. PLDI, 2000.
-
(2000)
PLDI
-
-
Bala, V.1
Duesterwald, E.2
Banerjia, S.3
-
12
-
-
84943422723
-
An infrastructure for adaptive dynamic optimization
-
Bruening, D., Garnett, T., and Amarasinghe, S: An infrastructure for adaptive dynamic optimization. CGO, 2003.
-
(2003)
CGO
-
-
Bruening, D.1
Garnett, T.2
Amarasinghe, S.3
-
13
-
-
31944440969
-
Pin: Building customized program analysis tools with dynamic instrumentation
-
June
-
Luk, C.-K., Cohn, R., Muth, R., Patil, H., Klauser, A., Lowney, G., Wallace, S., Reddi, V. J., Hazelwood, K.: Pin: Building Customized Program Analysis Tools with Dynamic Instrumentation. PLDI, June 2005.
-
(2005)
PLDI
-
-
Luk, C.-K.1
Cohn, R.2
Muth, R.3
Patil, H.4
Klauser, A.5
Lowney, G.6
Wallace, S.7
Reddi, V.J.8
Hazelwood, K.9
-
14
-
-
33845324299
-
-
Technical Report 04-044, Computer Science, U. of Minnesota
-
Saxena, A., Hsu, W.-C.,: Dynamic Register Allocation for ADORE Runtime Optimization System. Technical Report 04-044, Computer Science, U. of Minnesota, 2004
-
(2004)
Dynamic Register Allocation for ADORE Runtime Optimization System
-
-
Saxena, A.1
Hsu, W.-C.2
-
15
-
-
84941187910
-
-
2
-
Intel®Itanium®Architecture, Software Developer's Manual, Volume 1, 2 and 3: http://www.intel.com/design/itanium/manuals/iiasdmanual.htm.
-
Software Developer's Manual
, vol.1-3
-
-
-
17
-
-
84949521500
-
Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines
-
Jesshope, C. R.: Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines. Proc. ACSAC 2001, Australia Computer Science Communications, Vol 23, No 4., pp80-88
-
Proc. ACSAC 2001, Australia Computer Science Communications
, vol.23
, Issue.4
, pp. 80-88
-
-
Jesshope, C.R.1
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