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Volumn 2005, Issue , 2005, Pages 28-32

Design methodology for memory-efficient multi-standard baseband processors

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SOFTWARE; DATA TRANSFER; ENERGY UTILIZATION; RADIO SYSTEMS; STORAGE ALLOCATION (COMPUTER);

EID: 33845288973     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APCC.2005.1554012     Document Type: Conference Paper
Times cited : (6)

References (9)
  • 1
    • 0038306552 scopus 로고    scopus 로고
    • A single-chip 802.11a MAC/PHY with a 32b RISC processor
    • Feb.
    • T. Fujitsawa et al., A Single-Chip 802.11a MAC/PHY with a 32b RISC Processor, ISSCC Dig. Tech. Papers, pp. 144-145, Feb. 2003.
    • (2003) ISSCC Dig. Tech. Papers , pp. 144-145
    • Fujitsawa, T.1
  • 5
    • 0036475789 scopus 로고    scopus 로고
    • Single chip programmable baseband ASSP for 5 GHz wireless LAN applications
    • February
    • J. Kneip et.al. Single Chip Programmable Baseband ASSP for 5 GHz Wireless LAN Applications, IECICE Trans. Electron., vol.E85-C, No.2 February 2002.
    • (2002) IECICE Trans. Electron. , vol.E85-C , Issue.2
    • Kneip, J.1
  • 6
    • 0037250637 scopus 로고    scopus 로고
    • A software-defined communications baseband chip
    • January
    • J. Glossner et al, A Software-Defined Communications Baseband Chip, IEEE Communications Magazine, January 2003.
    • (2003) IEEE Communications Magazine
    • Glossner, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.