A single-chip 802.11a MAC/PHY with a 32b RISC processor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Fujisawa, Toshio ^a   Hasegawa, Jun ^a   Tsuchie, Koji ^a   Shiozawa, Tatsuya ^a   Fujita, Tetsuya ^a   Seki Fukuda, Keiko ^a   Higashi, Tatsuya ^a   Bandai, Ryouichi ^a   Yoshida, Noboru ^a   Shinohara, Kaoru ^a   Watanabe, Tomohisa ^a   Hatano, Hiroshi ^a   Noguchi, Kiyoshi ^a   Saito, Toshitada ^a   Unekawa, Yasuo ^a   Aikawa, Takeshi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; EQUALIZERS; GAIN CONTROL; INTEGRATED CIRCUIT MANUFACTURE; INTERFACES (COMPUTER); QUEUEING THEORY; STANDARDS;

ADAPTIVE EQUALIZER; AUTOMATIC GAIN CONTROL; HARDWARE CENTRIC QUEING ARCHITECTURE; MULTIPATH FADING; PROCESSING CHIP; RIPPLE CANCELLATION COMPARATOR; SUBCARRIER PHASE ERRORS;

MICROPROCESSOR CHIPS;

EID: 0038306552     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)

1. J. Thomson et al., "An Integrated 802.11a Baseband and MAC Processor," ISSCC Digest of Technical Papers, pp. 126-127, Feb. 2002.