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Volumn , Issue , 2004, Pages 644-649
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An accelerator architecture for programmable multi-standard baseband processors
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Author keywords
CDMA; DSP; OFDM; SDR
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Indexed keywords
BANDWIDTH;
CODE DIVISION MULTIPLE ACCESS;
COMPUTER ARCHITECTURE;
ERROR CORRECTION;
LOCAL AREA NETWORKS;
NATURAL FREQUENCIES;
ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING;
SIGNAL PROCESSING;
COMMUNICATION STANDARDS;
DSP;
PROGRAMMABLE BASEBAND PROCESSORS;
SDR;
RADIO SYSTEMS;
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EID: 11144287752
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (3)
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References (13)
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