TETA: Transistor-level waveform evaluation for timing analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 21, Issue 5, 2002, Pages 605-616

  Acar, Emrah ^a,b,c   Dartu, Florentin ^a,d   Pileggi, Lawrence T ^a,e  

^a IEEE   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

^c IBM AUSTIN RESEARCH LABORATORY   (United States)

^d INTEL CORPORATION   (United States)

^e CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Circuit simulation; Interconnect; Timing analysis; Transient analysis

Indexed keywords

INTERCONNECT MODELS; RUNTIME EFFICIENCY; TIMING ANALYSIS; TRANSIENT ANALYSIS;

ALGORITHMS; CAPACITORS; COMPUTER AIDED LOGIC DESIGN; COMPUTER SIMULATION; DIGITAL CIRCUITS; GENERAL PURPOSE COMPUTERS; LOGIC GATES; MATHEMATICAL MODELS; MATRIX ALGEBRA; PIECEWISE LINEAR TECHNIQUES; WAVEFORM ANALYSIS;

INTEGRATED CIRCUIT TESTING;

EID: 0036575043     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.998631     Document Type: Article

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