The effect of wafer substrate resistance on inter poly oxide thickness variation

ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings

Volumn 2006, Issue , 2006, Pages 395-399

  Towner, Janet M ^a   Naughton, John J ^a  

^a ON SEMICONDUCTOR   (United States)

Author keywords

Capacitor oxide; Electrostatic charging; PECVD TEOS deposition

Indexed keywords

CAPACITORS; ELECTROSTATICS; PLASMAS; ROBOTICS; SILICON WAFERS; SUBSTRATES;

CAPACITOR OXIDE; ELECTROSTATIC CHARGING; PECVD TEOS DEPOSITION;

SEMICONDUCTOR DEVICES;

EID: 33751404346     PISSN: 10788743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASMC.2006.1638790     Document Type: Conference Paper

References (6)

1. W. Lukaszek, "Wafer Charging Damage in IC Process Equipment," ECS Int. Semi. Tech. Conf. (2001).
2. Z. Xu, C. Bencher, M. Le and C. Ngai, "Plasma Damage Monitoring for PECVD Deposition: A Contact Potential Difference Study and Device Yield Analysis" SPIE Conf. Vol. 3509, p. 147 (1998).
3. A. Cacciato "Minimizing the Effects of Hardware Marginality on Charging Damage during Plasma Enhanced Chemical Vapor Dielectric Deposition" J. of the Electrochemical Society, vol. 148, p. F207 (2001).
4. J. K. Lan, Y. Wang, C.G. Chao, K. Lo, Y.L. Cheng "Effect of substrate on the step coverage of plasma enhanced chemical vapor deposition" J.Vac. Sci. Technol. B 21(4) (2003).
5. K.P. Cheung and C.-S. Pai, "Charging Damage from Plasma Enhanced TEOS Deposition" IEEE Electron Device Letters, vol. 16, p. 220 (1995).
6. L.B. Levit and J. Menear, "Measuring and Quantifying Static Charge in Cleanrooms and Process Tools," Solid State Technology 41, no. 2 (1998): 85-92