Job releasing and throughput planning for wafer fabrication under demand fluctuating make-to-stock environment

International Journal of Advanced Manufacturing Technology

Volumn 31, Issue 3-4, 2006, Pages 316-327

  Chung, Shu Hsing ^a   Lai, Chun Mei ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Cycle time; Lot release scheduling; Product mix; Wafer fabrication

Indexed keywords

COMPUTER SIMULATION; INVENTORY CONTROL; PRODUCTION CONTROL; SCHEDULING; STRATEGIC PLANNING; THROUGHPUT; WSI CIRCUITS;

CYCLE TIME; LOT RELEASE SCHEDULING; PRODUCT MIX; WAFER FABRICATION;

JOB ANALYSIS;

EID: 33751120379     PISSN: 02683768     EISSN: 14333015     Source Type: Journal    
DOI: 10.1007/s00170-005-0185-8     Document Type: Article

References (19)

1. Chou YC, Hong IH (2000) A methodology for product mix planning in semiconductor foundry manufacturing. IEEE Trans Semicond Manuf 13(3):278-285
2. Dümmler MA (2000) Analysis of the instationary behavior of a wafer fab during product mix changes. Proc 2000 Winter Simulation Conference, pp 1436-1442
3. Sivakumar AI, Chong CS (2001) A simulation based analysis of cycle time distribution, and throughput in semiconductor backend manufacturing. Comput Ind 45:59-78
4. Lu SCH, Ramaswamy D, Kumar PR (1994) Efficient scheduling policies to reduce mean and variance of cycle-time in semiconductor manufacturing plants. IEEE Trans Semicond Manuf 7(3):374-388
5. Lawrence SR (1995) Estimating flow times and setting due-dates in complex production systems. IIE Trans 27(5):657-668
6. Matsuyama A, Atherton RW (1990) Experience in simulation wafer fabs in the USA and Japan. 1990 International Semiconductor Manufacturing Science Symposium
7. Glynn PM, O'Dea M (1997) How to get predictable throughput times in a multiple product environment. Semiconductor Manufacturing Conference Proc, 1997 IEEE International Symposium, pp 27-30
8. Raddon A, Grigsby B (1997) Throughput time forecasting model. 1997 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp 430-433
9. Chung SH, Huang HW (1999) The block-based cycle time estimation algorithm for wafer fabrication factories. Int J Ind Eng 6(4):307-316
10. Liu C, Thongmee S, Hepburn P (1995) A methodology for improving on-time delivery and load levelling starts. Proc IEEE/SEMI Advanced Semiconductor Manufacturing Conference, pp 95-100
11. Hackman ST, Leachman RC (1989) A general framework for modeling production. Manage Sci 35(4):478-495
12. Chu SCK (1995) A mathematical programming approach towards optimized master production scheduling. Int J Prod Econ 38:269-270
13. Burman DY, Gurrola-Gal F, Nozari JA, Sathaye S, Sitarik JP (1986) Performance analysis techniques for IC manufacturing lines. AT&T Technical J, pp 46-56
14. Thompson SD, Davis WJ (1990) An integrated approach for modeling uncertainty in aggregate production planning. IEEE Trans Syst Man Cybern 20:1000-1012
15. Hung YF, Leachman RC (1996) A production planning methodology for semiconductor manufacturing based on interactive simulation and linear programming calculations. IEEE Trans Semicond Manuf 9(2):257-269
16. Hood SJ, Bermon S, Barahona F (2003) Capacity planning under demand uncertainty for semiconductor manufacturing. IEEE Trans Semicond Manuf 16(2):273-280
17. Chung SH, Yang MH, Cheng CM (1997) The design of due-date assignment model and the determination of flow time control parameter for the wafer fabrication factories. IEEE Trans Compon, Packag, Manuf Technol 20:278-287
18. Little JDC (1961) A proof for the queueing formula L=L=λW. Oper Res 9:383-387
19. Tecnomatix Technologies Ltd. (2000) eM-plant pbjects manual. Tecnomatix Software Company, Germany