Block-based cycle time estimation algorithm for wafer fabrication factories

International Journal of Industrial Engineering : Theory Applications and Practice

Volumn 6, Issue 4, 1999, Pages 307-316

  Chung, Shu Hsing ^a   Huang, Hung Wen ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; COMPUTER WORKSTATIONS; ESTIMATION; PERFORMANCE; QUEUEING THEORY;

BLOCK BASED CYCLE TIME; WAFER FABRICATION FACTORIES;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0033438122     PISSN: 10724761     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (6)

1. Banks, J., (1984). Discrete-Event System Simulation, Prentice-Hall, Inc.
2. Conway, R., Maxwell, W., and L. W. Miller, (1967). Theory of Scheduling, Addison-Wesley Publishing Company, Inc.
3. Ehteshami, B., et al., (1992). Trade-Offs in Cycle Time Management: Hot Lots, IEEE Transactions on Semiconductor Manufacturing, May: 101-105.
4. Kramer, Scott S., (1989). Total Cycle Time Management by Operational Elements, International Semiconductor Manufacturing Science Symposium, 17-20.
5. Martin, D. P., (1998). How the Law of Unanticipated Consequences can Nullify the Theory of Constraint: The Case for Balanced Capacity in a Semiconductor Manufacturing Line, Semiconductor FABTECH, Seventh Edition, ICG publishing Ltd, 29-34.
6. Su, Yu-Chang, (1998). The Construction of Production Planning and Scheduling System for an IC Foundry in Ramp-up, the thesis of Industrial Engineering and Management Department in National Chiao Tung University.