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Volumn 2006, Issue , 2006, Pages 184-189

Single event transients in dynamic logic

Author keywords

Dynamic logic; Integrated circuits; Single event transients

Indexed keywords

COMPUTATIONAL METHODS; COMPUTER SIMULATION; DATA STORAGE EQUIPMENT; INFORMATION RETRIEVAL; MATHEMATICAL MODELS; RADIATION EFFECTS; SIGNAL PROCESSING;

EID: 33750908730     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1150343.1150392     Document Type: Conference Paper
Times cited : (6)

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  • 3
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    • (2001) IEEE Trans. Nucl. Sci. , vol.48 , pp. 225-231
    • Palau, J.1    Hubert, G.2    Coulie, K.3    Sagnes, B.4    Calvet, M.5
  • 5
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    • (1996) IBM Journal of R&D , vol.40 , Issue.1 , pp. 19-40
    • Ziegler, J.F.1
  • 6
    • 0020298427 scopus 로고
    • Collection of charge on junction nodes from ion tracks
    • G C Messenger, "Collection of Charge on Junction Nodes from Ion Tracks", IEEE Trans. Nucl. Sci., vol. NS-29, pp. 2024-2031, 1982.
    • (1982) IEEE Trans. Nucl. Sci. , vol.NS-29 , pp. 2024-2031
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  • 7
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    • Modeling the cosmic-ray-induced soft-error rate in ICs: An overview
    • G R Srinivasan, "Modeling the Cosmic-Ray-Induced Soft-Error Rate in ICs: An Overview", IBM Journal of R&D, Vol. 40, No. 1, pp. 77-90, 1996.
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    • A gate-level simulation environment for alpha-particle-induced transient faults
    • H Cha, E M Rudnick, J H Patel, R K Iyer and G S Choi, "A Gate-Level Simulation Environment for Alpha-Particle-Induced Transient Faults". IEEE Trans. on Computers, Vol. 45, pp. 1248-1256, 1996.
    • (1996) IEEE Trans. on Computers , vol.45 , pp. 1248-1256
    • Cha, H.1    Rudnick, E.M.2    Patel, J.H.3    Iyer, R.K.4    Choi, G.S.5
  • 13
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    • http://www-device.eecs.berkeley.edu/~ptm
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    • Interconnect and noise immunity design for the pentium 4 processor
    • Feb.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.