On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives

SBCCI 2006 - 19th Symposium on Integrated Circuits and Systems Design

Volumn 2006, Issue , 2006, Pages 173-178

  Paulsson, K ^a   Hubner M ^a   Becker, J ^a  

^a UNIVERSITY OF KARLSRUHE   (Germany)

Author keywords

Dynamic and partial FPGA reconfiguration; On line adaptation; Power dissipation

Indexed keywords

ENERGY DISSIPATION; FIELD PROGRAMMABLE GATE ARRAYS; MICROPROCESSOR CHIPS; MULTIMEDIA SYSTEMS; ROUTERS; SIGNAL PROCESSING;

DYNAMIC AND PARTIAL FPGA RECONFIGURATION; ONLINE ADAPTATION; ONLINE OPTIMIZATION; POWER DISSIPATION;

COMMUNICATION SYSTEMS;

EID: 33750906745     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1150343.1150389     Document Type: Conference Paper

References (9)

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3. M. Ullmann, M. Hübner, B. Grimm, J. Becker,"An FPGA Run-Time System for Dynamical On-Demand Reconfiguration," Proc. of the 11th Reconfigurable Architectures Workshop (RAW/IPDPS), April 2004.
4. Xilinx Web Site. On-line at www.xilinx.com.
5. M. Huebner, T. Becker, J. Becker: "Real-time LUT-based Network Topologies for dynamic and partial FPGA Self-Reconfiguration", SBCCI04, Porto de Galinhas, Brasil.
6. M.Hübner, C. Schuck, M. Kühnle, J. Becker: "New 2-Dimensional Partial Dynamic Reconfiguration Techniques for Real-Time Adaptive Microelectronic Circuits", ISVLSI2006, Karlsruhe, Germany.
7. K. W. W. Poon, "Power Estimation for Field Programmable Gate Arrays," Master of Applied Science Dissertation, University of British Colombia, 2002.
8. B. Blodget, S. McMillan: "A lightweight approach for embedded reconfiguration of FPGAs", DATE'03, Munich Germany.
9. J. Becker, M. Hübner, K. Paulsson, A. Thomas: "Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics", ReCoSoC 2005, Montpellier, France.