A new on-chip substrate-coupled inductor model implemented with scalable expressions

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 11, 2006, Pages 2491-2498

  Lai, Ivan C H ^a,b   Fujishima, Minoru ^a,b  

^a IEEE   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

CMOS; Equivalent terminal resistance; Modeling; On chip inductors; Quality factor

Indexed keywords

EQUIVALENT TERMINAL RESISTANCE; MODELING; MONOMIAL EQUATIONS; ON-CHIP INDUCTORS; QUALITY FACTORS;

CHIP SCALE PACKAGES; EXTRAPOLATION; INDUCTANCE; INTEGRATED CIRCUITS; Q FACTOR MEASUREMENT; SILICON ON INSULATOR TECHNOLOGY;

ELECTRIC INDUCTORS;

EID: 33750817272     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.883320     Document Type: Conference Paper

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