Accurate subcircuit model of an on-chip inductor with a new substrate network

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2004, Pages 376-379

  Fujishima, Minoru ^a   Kino, Jun ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DATA ACQUISITION; EDDY CURRENTS; INTEGRATED CIRCUITS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; NATURAL FREQUENCIES; SIGNAL PROCESSING;

EQUIVALENT TERMINAL RESISTANCE (ETR); ON-CHIP INDUCTORS; PARASITIC CAPACITANCES; QUALITY FACTORS;

ELECTRIC INDUCTORS;

EID: 4544329004     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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