Dynamic flip-flop with improved power

European Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 376-379

  Nedovic, Nikola ^a   Oklobdzija, Vojin G ^a  

^a University of California Davis   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC FLIP-FLOPS; IMPROVED DESIGNS; POWER-DELAY PRODUCTS;

FLIP FLOP CIRCUITS;

PRODUCT DESIGN;

EID: 33750591622     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. F. Klass, "Semi-Dynamic and Dynamic Flip-Flops with Embedded Logic," Symp. on VLSI Circ, Digest of Technical Papers, June 1998
2. H. Partovi, et. al., "Flow-Through Latch and Edge-Triggered Flip-Flop Hybrid Elements," ISSCC Digest of Technical Papers, February 1996
3. V. Stojanovic, V. G. Oklobdzija, "Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems ", IEEE Journal of Solid-State Circuits, April 1999.