High-Speed Parallel CRC Implementation Based on Unfolding, Pipelining, and Retiming

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 53, Issue 10, 2006, Pages 1017-1021

  Cheng, Chao ^a   Parhi, Keshab K ^a  

^a University of Minnesota   (United States)

Author keywords

Cyclic redundancy check (CRC); linear feedback shift register (LFSR); pipelining; retiming unfolding; unfolding

Indexed keywords

ALGORITHMS; FEEDBACK; PIPELINE PROCESSING SYSTEMS; POLYNOMIALS; REDUNDANCY; SHIFT REGISTERS;

CYCLIC REDUNDANCY CHECK (CRC); HIGH-SPEED PARALLEL CIRCUITS; LINEAR FEEDBACK SHIFT REGISTER (LFSR);

PARALLEL PROCESSING SYSTEMS;

EID: 33750588104     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2006.882213     Document Type: Article

References (6)

1. T.-B. Pei and C. Zukowski, “High-speed parallel CRC circuits in VLSI,” IEEE Trans. Commun., vol. 40, no. 4, pp. 653–657, Apr. 1992
2. G. Campobello, G. Patané, and M. Russo, “Parallel CRC realization,” IEEE Trans. Comput., vol. 52, no. 10, pp. 1312–1319, Oct. 2003
3. K. K. Parhi, “Eliminating the fanout bottleneck in parallel long BCH encoders,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 3, pp. 512–516, Mar. 2004
4. X. Zhang and K. K. Parhi, “High-speed architectures for parallel long BCH encoders,” in Proc. ACM Great Lakes Symp. VLSI, Boston, MA, Apr. 2004, pp. 1–6
5. K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation. Hoboken, NJ: Wiley, 1999
6. T. V. Ramabadran and S.S. Gaitonde, “A tutorial on CRC computations,” IEEE Micro, vol. 8, no. 4, pp. 62–75, Aug. 1988