Thermal fatigue life time prediction of Sn-3.5 Ag lead-free solder joint for chip scale package

Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors

Volumn 27, Issue 9, 2006, Pages 1695-1700

  Han, Xiao ^a   Ding, Han ^a   Sheng, Xinjun ^a   Zhang, Bo ^a  

^a SHANGHAI JIAO TONG UNIVERSITY   (China)

Author keywords

Anand constitutive model; Chip scale package; Fatigue life; Finite element analysis; Lead free solder joint

Indexed keywords

FATIGUE OF MATERIALS; FINITE ELEMENT METHOD; SIMULATION; SOLDERING ALLOYS; STRESS ANALYSIS; THERMAL CYCLING; THERMAL STRESS; THREE DIMENSIONAL;

ANAND CONSTITUTIVE MODEL; LEAD FREE SOLDER JOINT; THERMAL FATIGUE LIFE TIME;

CHIP SCALE PACKAGES;

EID: 33750581820     PISSN: 02534177     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (9)

1. Lee W W, Nguyen L T, Selvaduray G S. Solder joint fatigue models: review and applicability to chip scale package. Microelectron Reliab, 2000, 40: 231.
2. Xu Yangjian, Liu Yong, Liang Lihua, et al. Life prediction for solder joint interconnect in the package-strain energy density methodology and effective strain methodology. Chinese Journal of Applied Mechanics, 2005, 22(2): 279 (in Chinese).
3. Darveaux R. Effect of simulation methodology on solder joint crack growth correlation. Proceedings of 50th Electronic Components and Technology Conference, 2000: 1048.
4. He Ping, Peng Yaowei, Wu Jianbo, et al. Solder joint fatigue reliability of vf-BGA package. Chinese Journal of Semiconductors, 2004, 25(7): 874 (in Chinese).
5. Zahn B A. Finite element based solder joint fatigue life predictions for a same die size-stacked-chip scale-ball grid array package. Proceedings of SEMI/IEEE International Electronics Manufacturing Technology Symposium, 2002: 274.
6. Lall P, Islam M N, Singh N, et al. Model for BGA and CSP reliability in automotive underhood applications. IEEE Transactions on Components and Packaging Technologies, 2004, 27(3): 585.
7. Chen X, Chen G, Sakane M. Prediction of stress-strain relationship with an improved Anand constitutive model for lead-free solder Sn-3.5 Ag. IEEE Transactions on Components and Packaging Technologies, 2005, 28(1): 111.
8. Lau J H, Lee S W R. Modeling and analysis of 96.5 Sn-3.5 Ag lead-free solder joints of wafer level chip scale package on buildup microvia printed circuit board. IEEE Transactions on Electronics Packaging Manufacturing, 2002, 25(1): 51.
9. Ase Kaohsiung. CSP VFBGA. 2005. http://www.asetwn.com.tw/content/2-4-1.html. Cited 20 Jan 2006.