Satisfying timing constraints of preemptive real-time tasks through task layout technique

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2001, Pages 97-102

  Datta, Anupam ^a   Choudhury, Sidharth ^a   Basu, Anupam ^a   Tomiyama, Hiroyuki ^b   Dutt, Nikil ^b  

^a INDIAN INSTITUTE OF TECHNOLOGY   (India)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE FILTERING; CACHE MEMORY; DIGITAL SIGNAL PROCESSING; FIR FILTERS; MATRIX ALGEBRA; MULTITASKING; RESPONSE TIME (COMPUTER SYSTEMS);

CACHE RELATED PREEMPTION DELAY (CRPD); WORST CASE RESPONSE TIME (WCRT);

REAL TIME SYSTEMS;

EID: 0035007992     PISSN: 10639667     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICVD.2001.902646     Document Type: Article

References (0)