Absolute and relative fatigue life prediction methodology for virtual qualification and design enhancement of lead-free BGA

Proceedings - Electronic Components and Technology Conference

Volumn 2, Issue , 2005, Pages 1282-1291

  Ng, Hun Shen ^a   Tee, Tong Yan ^a   Goh, Kim Yong ^a   Luan, Jing En ^a   Reinikainen, Tommi ^b   Hussa, Esa ^b   Kujala, Arni ^b  

^a STMICROELECTRONICS   (Singapore)

^b NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CREEP MODELS; EUTECTIC SOLDER; LEAD-FREE SOLDERS; PACKAGE DIMENSIONS;

CREEP; ELECTRONICS PACKAGING; EUTECTICS; FATIGUE OF MATERIALS; FINITE DIFFERENCE METHOD; LEAD ALLOYS; SEMICONDUCTOR DEVICE MANUFACTURE; TIN ALLOYS;

SOLDERING ALLOYS;

EID: 24644514557     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (42)

1. rd ASEAN ANSYS Conference Proc., Singapore, 2000, pp. 22-24.
2. nd EMAP Conference, Hong Kong, 2000, pp. 51-54.
3. Tee, T.Y., Ng, H.S., Sivakumar, K., Diot, J., Frezza, G., Tiziani, R., and Santospirito, G., "Board Level Solder Joint Reliability Modeling and Testing of QFN Package," ICMAT Conference Proc., Singapore, 2001.
4. Tee, T.Y., Ng, H.S., and Pan, S., "Board Level Solder Joint Reliability Modeling of TFBGA Package," ICEP Conference Proc., Japan, 2002, pp. 492-497.
5. nd ECTC Conference Proc., 2002, pp. 985-991.
6. th ASEAN ANSYS Conference Proc., Singapore, 2002.
7. th EPTC Conference Proc., Singapore, 2002, pp. 391-397.
8. Tee, T.Y., Lim, M., Ng, H.S., Baraton, X., and Zhong, Z.W., "Design Analysis and Optimization of Wirebond Stacked Die BGA Packages for Improved Board Level Solder Joint Reliability," Keynote Paper, EuroSIME Conference Proc., France, 2003, pp. 207-213.
9. Tee, T.Y., "Board-level Reliability Design: Analysis of Three Types of 0.5mm Pitch CSPs," Advanced Packaging Magazine, June 2003, pp. 25-29.
10. Tee, T.Y., Ng, H.S., and Zhong, Z.W., "Design for Package and Board Level Reliability with CAE," Invited Paper, SEMICON Advanced Packaging Technology Symposium, Singapore, 2003, pp. 59-67.
11. Tee, T.Y., Ng, H.S., Yap, D., and Zhong, Z.W., "Board Level Solder Joint Reliability Modeling and Testing of Fine-pitch CSP Packages for Telecommunication Applications," SEMICON Advanced Packaging Technology Symposium, Singapore, 2003, pp. 31-36.
12. rd ECTC Conference Proc., 2003, pp. 1869-1874.
13. Tee, T.Y., Zhou, T., Lim, M., and Zhong Z.W., "Design Analysis of Board Level Solder Reliability for Thermally Enhanced BGAs," SMTA Conference, Chicago, USA, 2003, pp. 374-380.
14. Tee, T.Y., Ng, H.S., Yap, D., Baraton, X., and Zhong, Z.W., "Board Level Solder Joint Reliability Modeling and Testing of TFBGA Packages for Telecommunication Applications," Microelectronics Reliability Journal, 2003, Vol. 43(7), pp. 1117-1123.
15. Tee, T.Y., Ng, H.S., Yap, D., and Zhong, Z.W., "Comprehensive Board-Level Solder Joint Reliability Modeling and Testing of QFN and PowerQFN Packages," Microelectronics Reliability Journal, 2003, Vol. 43(8), pp. 1329-1338.
16. Diot, J., Loo, K.W., Moscicki, J., Ng, H.S., Tee, T.Y., Teysseyre, J., and Yap, D., "New Package for C-MOS Sensors," SPIE Conference Proc., Optical System Design, France, 2003.
17. Tee, T.Y., Frezza, G., Lim, M., Ng, H.S., Ziglioli, F., and Zhong, Z.W., "Design for Board Level Reliability of a Miniaturized MEMS Package: Stacked Die TQFN," International Journal of Computational Engineering Science (IJCES), 2003, Vol. 4(2), pp. 347-350.
18. th EMAP Conference Proc., Singapore, 2003, pp. 184-189.
19. th EMAP Conference Proc., Singapore, 2003, pp. 309-315.
20. th EPTC Conference, Singapore, 2003, pp. 210-216.
21. Ng, H.S., Lim, M., Tee, T.Y., "Design for Enhanced Board Level Solder Joint Reliability of Very High Pin Count FCBGA Package", ICEP Conference, Japan, 2004, pp. 313-318.
22. Tee, T.Y., Ng, H.S., Luan, J.E., Yap, D., Loh, K., Pek, E., Lim, C.T., and Zhong, Z.W., "Integrated Modeling and Testing of Fine-pitch CSP under Board Level Drop Test, Bend Test and Thermal Cycling Test", ICEP Conference, Japan, 2004, pp. 35-40.
23. Lim, M., Tee, T.Y., Ng, H.S., Deodato, C., Tiziani, R., Diot, J., Chiu, A., and Zhong, Z.W., "Design Analysis of Multi-chip QFN Solder Joint Reliability", SEMICON Advanced Packaging Technology Symposium, Singapore, 2004, pp. 157-162.
24. Tee, T.Y., Lim, M., Ng, H.S., Baraton, X., Frezza, G., Chiu, A., and Zhong, Z.W., "Design for Enhanced Board Level Solder Joint Reliability of Stacked Die CSPs", Invited Paper, SEMICON Advanced Packaging Technology Symposium, Singapore, 2004, pp. 151-155.
25. Tee, T.Y., "Design for Reliability of Stacked Die CSPs," Advanced Packaging Magazine, July 2004, pp. 37-40.
26. Tee, T.Y., Hundt, M., and Cognetti, C., "4-Dimensional Design Optimization of System-in-Package with CAE," Topical Research Conference on Reliability (TRC), Austin, USA, 2004.
27. th EMAP Conference Proc., Malaysia, 2004, pp. 442-449.
28. th EPTC Conference Proc., Singapore, 2004, pp. 743-747.
29. Tee, T.Y. and Zhong, Z.W., "Board Level Solder Joint Reliability Analysis and Optimization of Pyramidal Stacked Die BGA Packages," Microelectronics Reliability Journal, 2004, Vol. 44(12), pp. 1957-1965.
30. Ibe, E., Loh, K., Luan, J.E., and Tee, T.Y., "Underfill Effects on BGA Drop, Bend, and Thermal Cycle Tests," Advanced Packaging Magazine, Feb. 2005, pp. 28-30.
31. Ng, H.S., Tee, T.Y., Goh, K.Y., Luan, J.E., Hussa, E., Reinikainen, T., and Kujala, A., "Fatigue Life Prediction Models for Lead-free BGA Packages and Modules," ICEP Conference Proc., Japan, April 2005.
32. Tee, T.Y. and Ng, H.S., "Design Analysis and Optimization of Flip-chip CSP Board Level Solder Joint Reliability", SEMICON Advanced Packaging Technology Symposium, Singapore, May 2005.
33. Tee, T.Y. Package and Board Level Reliability Modeling of Advanced CSP Packages for Telecommunication Applications, Ph.D. Thesis, Nanyang Technological University, Singapore, 2005, Chapters 5-6, pp. 66-125.
34. Darveaux, R., Banerji, K., Mawer, A., and Dody, G., "Reliability of Plastic Ball Grid Array Assembly," Ball Grid Array Technology, J. Lau Editor, McGraw-Hill, New York, 1995, pp. 379-442.
35. th ECTC Conference Proc., 2000, pp. 1048-1058.
36. Lee, W.W., Nguyen, L.T., and Selvaduray, G.S., "Solder Joint Fatigue Models - Review and Applicability to Chip Scale Packages," Microelectronics Reliability Journal, 2000, Vol. 40, pp. 231-244.
37. ANSYS User's Manual, Swanson Analysis Systems, Inc., 1994, Vol. IV, pp. 4.23-25.
38. Brown, S., Kim, K., and Anand, L., "An Internal Variable Constitutive Model for Hot Working of Metals", Int. J. Plasticity, 5, 1989, pp. 95-130.
39. Pang, J., Xiong, B.S., and Che, F.X., "Modeling Stress Strain Curves for Lead-Free 95.5Sn-3.8Ag-0.7Cu Solder", EuroSime Conference Proc., Belgium, 2004, pp. 449-454.
40. Reinikainen, T.O., Marjamäki, P., and Kivilahti, J.K., "Deformation Characteristics and Microstructural Evolution of SnAgCu Solder Joints," EuroSime Conference Proc., Germany, Apr. 2005.
41. rd ECTC 2003, pp. 197-206.
42. rd ECTC 2003, pp. 197-206.