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Volumn 2006, Issue , 2006, Pages 959-964

Statistical bellman-ford algorithm with an application to retiming

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DELAY CIRCUITS; GRAPH THEORY; PARAMETER ESTIMATION; PROCESS CONTROL; STATISTICAL METHODS;

EID: 33748617849     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118514     Document Type: Conference Paper
Times cited : (3)

References (16)
  • 1
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    • Impact of die-to-die and within-die paraemter fluctuations on
    • K. Bowman, S. Duvall, and J. Meindl, "Impact of die-to-die and within-die paraemter fluctuations on ..." in Proc. ISSCC, 2001.
    • (2001) Proc. ISSCC
    • Bowman, K.1    Duvall, S.2    Meindl, J.3
  • 2
    • 33748594045 scopus 로고    scopus 로고
    • Statistical timing analysis considering spatial correlations using
    • H. Chang and S. Sapatnekar, "Statistical timing analysis considering spatial correlations using ..." in Proc. ICCAD, 2003.
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    • Chang, H.1    Sapatnekar, S.2
  • 3
    • 33748613340 scopus 로고    scopus 로고
    • Statistical timing analysis using bounds and selective enumeration
    • A. Agarwal, V. Zolotov, and D. Blaauw, "Statistical timing analysis using bounds and selective enumeration," in IEEE TCAD, 2003.
    • (2003) IEEE TCAD
    • Agarwal, A.1    Zolotov, V.2    Blaauw, D.3
  • 6
    • 0026961616 scopus 로고
    • Computing optimal clock schedules
    • T. G. Szymanski, "Computing optimal clock schedules," in Proc. DAC., 1992.
    • (1992) Proc. DAC.
    • Szymanski, T.G.1
  • 7
    • 77956023701 scopus 로고    scopus 로고
    • An efficient verification method for a class of multi-phase sequential circuits
    • Y. S. F-R. Boyer, El M. Aboulhamd, "An efficient verification method for a class of multi-phase sequential circuits," in ICECS, 2000.
    • (2000) ICECS
    • Boyer, Y.S.F.-R.1    Aboulhamd, El.M.2
  • 8
    • 33748606749 scopus 로고    scopus 로고
    • Retiming-based timing analysis with an application to
    • J. Cong and S. K. Lim, "Retiming-based timing analysis with an application to ..." IEEE TCAD, vol. 23, no. 12, 2004.
    • (2004) IEEE TCAD , vol.23 , Issue.12
    • Cong, J.1    Lim, S.K.2
  • 11
    • 33748630876 scopus 로고
    • An algorithm to compact a vlsi symbolic layout with mixed constraints
    • Y.-Z. Liao and C. K. Wong, "An algorithm to compact a vlsi symbolic layout with mixed constraints," IEEE TCAD, 1983.
    • (1983) IEEE TCAD
    • Liao, Y.-Z.1    Wong, C.K.2
  • 12
    • 16244418078 scopus 로고    scopus 로고
    • Clock schedule verification under process variations
    • R. Chen and H. Zhou, "Clock schedule verification under process variations," in Proc. ICCAD, 2004.
    • (2004) Proc. ICCAD
    • Chen, R.1    Zhou, H.2
  • 15
    • 0001310038 scopus 로고
    • The greatest of a finite set of random variables
    • C. Clark, "The greatest of a finite set of random variables," in Operations Research, 1961.
    • (1961) Operations Research
    • Clark, C.1
  • 16
    • 84893771007 scopus 로고    scopus 로고
    • Statistical timing driven partitioning for vlsi circuits
    • C. Ababei and K. Bazargan, "Statistical timing driven partitioning for vlsi circuits," in Proc. DATE, 2002.
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    • Ababei, C.1    Bazargan, K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.