Methodology for fast FPGA floorplanning

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 1999, Pages 47-56

  Emmert, John M ^a   Bhatia, Dinesh ^a  

^a UNIVERSITY OF CINCINNATI   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC DESIGN; OPTIMIZATION;

MICRO BASED FLOORPLANNING; TABU SEARCH OPTIMIZATION;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0032636334     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (19)